General Purpose Transistor
NPN Silicon
MAXIMUM RATINGS
Rating Symbol Value Unit
Collector–Emitter Voltage VCEO 45 Vdc
Collector–Base Voltage VCBO 50 Vdc
Emitter–Base V oltage VEBO 5.0 Vdc
Collector Current — Continuous IC100 mAdc
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Total Device Dissipation FR–5 Board(1)
TA = 25°C
Derate above 25°C
PD225
1.8
mW
mW/°C
Thermal Resistance, Junction to Ambient RJA 556 °C/W
Total Device Dissipation
Alumina Substrate,(2) TA = 25°C
Derate above 25°C
PD300
2.4
mW
mW/°C
Thermal Resistance, Junction to Ambient RJA 417 °C/W
Junction and Storage Temperature TJ, Tstg –55 to +150 °C
DEVICE MARKING
BCW72LT1 = K2
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Collector–Emitter Breakdown Voltage
(IC = 2.0 mAdc, VEB = 0) V(BR)CEO 45 — — Vdc
Collector–Emitter Breakdown Voltage
(IC = 2.0 mAdc, VEB = 0) V(BR)CES 45 — — Vdc
Collector–Base Breakdown Voltage
(IC = 10 Adc, IE = 0) V(BR)CBO 50 — — Vdc
Emitter–Base Breakdown Voltage
(IE = 10 Adc, IC = 0) V(BR)EBO 5.0 — — Vdc
Collector Cutoff Current
(VCB = 20 Vdc, IE = 0)
(VCB = 20 Vdc, IE = 0, TA = 100°C)
ICBO —
——
—100
10 nAdc
Adc
1. FR–5 = 1.0 0.75 0.062 in.
2. Alumina = 0.4 0.3 0.024 in. 99.5% alumina.
ON Semiconductor
Semiconductor Components Industries, LLC, 2001
March, 2001 – Rev. 1 1Publication Order Number:
BCW72LT1/D
BCW72LT1
12
3
CASE 318–08, STYLE 6
SOT–23 (TO–236AB)
COLLECTOR
3
1
BASE
2
EMITTER
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ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) (Continued)
Characteristic Symbol Min Typ Max Unit
ON CHARACTERISTICS
DC Current Gain
(IC = 2.0 mAdc, VCE = 5.0 Vdc) hFE 200 — 450 —
Collector–Emitter Saturation Voltage
(IC = 10 mAdc, IB = 0.5 mAdc)
(IC = 50 mAdc, IB = 2.5 mAdc)
VCE(sat) —
——
0.21 0.25
—
Vdc
Base–Emitter Saturation Voltage
(IC = 50 mAdc, IB = 2.5 mAdc) VBE(sat) — 0.85 — Vdc
Base–Emitter On Voltage
(IC = 2.0 mAdc, VCE = 5.0 Vdc) VBE(on) 0.6 — 0.75 Vdc
SMALL–SIGNAL CHARACTERISTICS
Current–Gain — Bandwidth Product
(IC = 10 mAdc, VCE = 5.0 Vdc, f = 100 MHz) fT— 300 — MHz
Output Capacitance
(IE = 0, VCB = 10 Vdc, f = 1.0 MHz) Cobo — — 4.0 pF
Input Capacitance
(IE = 0, VCB = 10 Vdc, f = 1.0 MHz) Cibo — 9.0 — pF
Noise Figure
(IC = 0.2 mAdc, VCE = 5.0 Vdc, RS = 2.0 kΩ, f = 1.0 kHz,
BW = 200 Hz)
NF — — 10 dB
Figure 1. Turn–On Time Figure 2. Turn–Off Time
EQUIVALENT SWITCHING TIME TEST CIRCUITS
*Total shunt capacitance of test jig and connectors
10 k
+3.0 V
275
CS < 4.0 pF*
10 k
+3.0 V
275
CS < 4.0 pF*
1N916
300 ns
DUTY CYCLE = 2% +10.9 V
-0.5 V
<1.0 ns
10 < t1 < 500 µs
DUTY CYCLE = 2% +10.9 V
0
-9.1 V <1.0 ns
t1
TYPICAL NOISE CHARACTERISTICS
(VCE = 5.0 Vdc, TA = 25°C)
Figure 3. Noise Voltage
f, FREQUENCY (Hz)
5.0
7.0
10
20
3.0
Figure 4. Noise Current
f, FREQUENCY (Hz)
2.0
10 20 50 100 200 500 1k 2k 5k 10k
100
50
20
10
5.0
2.0
1.0
0.5
0.2
0.1
BANDWIDTH = 1.0 Hz
RS = 0
IC = 1.0 mA
100 µA
en, NOISE VOLTAGE (nV)
In, NOISE CURRENT (pA)
30 µA
BANDWIDTH = 1.0 Hz
RS ≈∞
10 µA
300 µA
IC = 1.0 mA
300 µA
100 µA
30 µA
10 µA
10 20 50 100 200 500 1k 2k 5k 10k
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NOISE FIGURE CONTOURS
(VCE = 5.0 Vdc, TA = 25°C)
Figure 5. Narrow Band, 100 Hz
IC, COLLECTOR CURRENT (µA)
500k
Figure 6. Narrow Band, 1.0 kHz
IC, COLLECTOR CURRENT (µA)
10
2.0 dB
BANDWIDTH = 1.0 Hz
RS, SOURCE RESISTANCE (OHMS)
RS, SOURCE RESISTANCE (OHMS)
Figure 7. Wideband
IC, COLLECTOR CURRENT (µA)
10
10 Hz to 15.7 kHz
RS, SOURCE RESISTANCE (OHMS)
Noise Figure is defined as:
NF 20 log10en24KTRSIn2RS2
4KTRS12
= Noise Voltage of the Transistor referred to the input. (Figure 3)
= Noise Current of the T ransistor referred to the input. (Figure 4)
= Boltzman’s Constant (1.38 x 10–23 j/°K)
= Temperature of the Source Resistance (°K)
= Source Resistance (Ohms)
en
In
K
T
RS
3.0 dB 4.0 dB
6.0 dB 10 dB
50
100
200
500
1k
10k
5k
20k
50k
100k
200k
2k
20 30 50 70 100 200 300 500 700 1k 10 20 30 50 70 100 200 300 500 700 1k
500k
100
200
500
1k
10k
5k
20k
50k
100k
200k
2k
1M
500k
50
100
200
500
1k
10k
5k
20k
50k
100k
200k
2k
20 30 50 70 100 200 300 500 700 1k
BANDWIDTH = 1.0 Hz
1.0 dB
2.0 dB 3.0 dB
5.0 dB
8.0 dB
1.0 dB
2.0 dB
3.0 dB
5.0 dB
8.0 dB
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TYPICAL STATIC CHARACTERISTICS
Figure 8. DC Current Gain
IC, COLLECTOR CURRENT (mA)
400
0.004
h , DC CURRENT GAIN
FE
TJ = 125°C
-55°C
25°C
VCE = 1.0 V
VCE = 10 V
Figure 9. Collector Saturation Region
IC, COLLECTOR CURRENT (mA)
1.4
Figure 10. Collector Characteristics
IC, COLLECTOR CURRENT (mA)
V, VOLTAGE (VOLTS)
1.0 2.0 5.0 10 20 50
1.6
100
TJ = 25°C
VBE(sat) @ IC/IB = 10
VCE(sat) @ IC/IB = 10
VBE(on) @ VCE = 1.0 V
*VC for VCE(sat)
VB for VBE
0.1 0.2 0.5
Figure 11. “On” Voltages
IB, BASE CURRENT (mA)
0.4
0.6
0.8
1.0
0.2
0
VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS)
0.002
TJ = 25°C
IC = 1.0 mA 10 mA 100 mA
Figure 12. Temperature Coefficients
50 mA
VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS)
40
60
80
100
20
0
0
IC, COLLECTOR CURRENT (mA)
TA = 25°C
PULSE WIDTH = 300 µs
DUTY CYCLE ≤ 2.0%
IB = 500 µA
400 µA
300 µA
200 µA
100 µA
*APPLIES for IC/IB ≤ hFE/2
25°C to 125°C
-55°C to 25°C
25°C to 125°C
-55°C to 25°C
40
60
0.006 0.01 0.02 0.03 0.05 0.07 0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50 70 100
0.005 0.01 0.02 0.05 0.1 0.2 0.5 1.0 2.0 5.0 10 20 5.0 10 15 20 25 30 35 40
1.2
1.0
0.8
0.6
0.4
0.2
0-2.4
0.8
0
-1.6
-0.8
1.0 2.0 5.0 10 20 50 10
0
0.1 0.2 0.5
200
100
80
V, TEMPERATURE COEFFICIENTS (mV/ C)°θ
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TYPICAL DYNAMIC CHARACTERISTICS
C, CAPACITANCE (pF)
Figure 13. Turn–On Time
IC, COLLECTOR CURRENT (mA)
300
Figure 14. Turn–Off Time
IC, COLLECTOR CURRENT (mA)
2.0 5.0 10 20 30 50
1000
Figure 15. Current–Gain — Bandwidth Product
IC, COLLECTOR CURRENT (mA)
Figure 16. Capacitance
VR, REVERSE VOLTAGE (VOLTS)
Figure 17. Input Impedance
IC, COLLECTOR CURRENT (mA)
Figure 18. Output Admittance
IC, COLLECTOR CURRENT (mA)
3.01.0
500
0.5
10
t, TIME (ns)
t, TIME (ns)
f, CURRENT-GAIN BANDWIDTH PRODUCT (MHz)
T
h , OUTPUT ADMITTANCE ( mhos)
oe
hie, INPUT IMPEDANCE (k )Ω
3.0
5.0
7.0
10
20
30
50
70
100
200
7.0 70 100
VCC = 3.0 V
IC/IB = 10
TJ = 25°C
td @ VBE(off) = 0.5 Vdc
tr
10
20
30
50
70
100
200
300
500
700
2.0 5.0 10 20 30 50
3.01.0 7.0 70 100
VCC = 3.0 V
IC/IB = 10
IB1 = IB2
TJ = 25°C
ts
tf
50
70
100
200
300
0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50
TJ = 25°C
f = 100 MHz
VCE = 20 V
5.0 V
1.0
2.0
3.0
5.0
7.0
0.1 0.2 0.5 1.0 2.0 5.0 10 20 500.05
TJ = 25°C
f = 1.0 MHz
Cib
Cob
2.0 5.0 10 20 50
1.0
0.2
100
0.3
0.5
0.7
1.0
2.0
3.0
5.0
7.0
10
20
0.1 0.2 0.5
hfe ≈ 200 @ IC = 1.0 mA
VCE = 10 Vdc
f = 1.0 kHz
TA = 25°C
2.0 5.0 10 20 50
1.0
2.0
100
3.0
5.0
7.0
10
20
30
50
70
100
200
0.1 0.2 0.5
VCE = 10 Vdc
f = 1.0 kHz
TA = 25°C
hfe ≈ 200 @ IC = 1.0 mA
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Figure 19. Thermal Response
t, TIME (ms)
1.0
0.01
r(t) TRANSIENT THERMAL RESISTANCE
(NORMALIZED)
0.01
0.02
0.03
0.05
0.07
0.1
0.2
0.3
0.5
0.7
0.02 0.05 0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100 200 500 1.0k 2.0k 5.0k 10k 20k 50k
100k
D = 0.5
0.2
0.1
0.05
0.02
0.01 SINGLE PULSE
DUTY CYCLE, D = t1/t2
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1 (SEE AN–569)
ZθJA(t) = r(t) •RθJA
TJ(pk) – TA = P(pk) ZθJA(t)
t1
t2
P(pk)
FIGURE 19A
Figure 19A.
TJ, JUNCTION TEMPERATURE (°C)
104
-40
IC, COLLECTOR CURRENT (nA)
Figure 20.
VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS)
400
2.0
IC, COLLECTOR CURRENT (mA)
DESIGN NOTE: USE OF THERMAL RESPONSE DATA
A train of periodical power pulses can be represented by the model
as shown in Figure 19A. Using the model and the device thermal
response the normalized effective transient thermal resistance of
Figure 19 was calculated for various duty cycles.
To find ZθJA(t), multiply the value obtained from Figure 19 by the
steady state value RθJA.
Example:
The MPS3904 is dissipating 2.0 watts peak under the following
conditions:
t1 = 1.0 ms, t2 = 5.0 ms. (D = 0.2)
Using Figure 19 at a pulse width of 1.0 ms and D = 0.2, the reading of
r(t) is 0.22.
The peak rise in junction temperature is therefore
∆T = r(t) x P(pk) x RθJA = 0.22 x 2.0 x 200 = 88°C.
For more information, see AN–569.
The safe operating area curves indicate IC–VCE limits of the
transistor that must be observed for reliable operation. Collector load
lines for specific circuits must fall below the limits indicated by the
applicable curve.
The data of Figure 20 is based upon TJ(pk) = 150°C; TC or TA is
variable depending upon conditions. Pulse curves are valid for duty
cycles to 10% provided TJ(pk) ≤ 150°C. TJ(pk) may be calculated from
the data in Figure 19. At high case or ambient temperatures, thermal
limitations will reduce the power that can be handled to values less
than the limitations imposed by second breakdown.
10-2
10-1
100
101
102
103
-20 0 +20 +40 +60 +80 +100 +120 +140 +160
VCC = 30 Vdc
ICEO
ICBO
AND
ICEX @ VBE(off) = 3.0 Vdc
TA = 25°C
CURRENT LIMIT
THERMAL LIMIT
SECOND BREAKDOWN LIMIT
1.0 ms
10 µs
TC = 25°C1.0 s
dc
dc
4.0
6.0
10
20
40
60
100
200
4.0 6.0 8.0 10 20 40
TJ = 150°C
100 µs
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INFORMATION FOR USING THE SOT–23 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must
be the correct size to insure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
SOT–23
mm
inches
0.037
0.95
0.037
0.95
0.079
2.0
0.035
0.9
0.031
0.8
SOT–23 POWER DISSIPATION
The power dissipation of the SOT–23 is a function of the
pad size. This can vary from the minimum pad size for
soldering to a pad size given for maximum power
dissipation. Power dissipation for a surface mount device is
determined by TJ(max), the maximum rated junction
temperature o f the die, RθJA, the thermal resistance from t h e
device junction to ambient, and the operating temperature,
TA. Using the values provided on the data sheet for the
SOT–23 package, PD can be calculated as follows:
PD = TJ(max) – TA
RθJA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature TA of 25°C, one can
calculate the power dissipation of the device which in this
case is 225 milliwatts.
PD = 150°C – 25°C
556°C/W = 225 milliwatts
The 556°C/W for the SOT–23 package assumes the use of
the recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 225 milliwatts.
There are other alternatives to achieving higher power
dissipation from the SOT–23 package. Another alternative
would be to use a ceramic substrate or an aluminum core
board such as Thermal Clad. Using a board material such
as Thermal Clad, an aluminum core board, the power
dissipation can be doubled using the same footprint.
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within
a short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
•Always preheat the device.
•The delta temperature between the preheat and soldering
should be 100°C or less.*
•When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering method,
the difference shall be a maximum of 10°C.
•The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
•When shifting from preheating to soldering, the maximum
temperature gradient shall be 5°C or less.
•After soldering has been completed, the device should be
allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and result
in latent failure due to mechanical stress.
•Mechanical stress or shock should not be applied during
cooling.
* Soldering a device without preheating can cause
excessive thermal shock and stress which can result in
damage to the device.
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PACKAGE DIMENSIONS
CASE 318–08
ISSUE AF
SOT–23 (TO–236)
DJ
K
L
A
C
BS
H
GV
3
12
DIM
A
MIN MAX MIN MAX
MILLIMETERS
0.1102 0.1197 2.80 3.04
INCHES
B0.0472 0.0551 1.20 1.40
C0.0350 0.0440 0.89 1.11
D0.0150 0.0200 0.37 0.50
G0.0701 0.0807 1.78 2.04
H0.0005 0.0040 0.013 0.100
J0.0034 0.0070 0.085 0.177
K0.0140 0.0285 0.35 0.69
L0.0350 0.0401 0.89 1.02
S0.0830 0.1039 2.10 2.64
V0.0177 0.0236 0.45 0.60
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD THICKNESS
IS THE MINIMUM THICKNESS OF BASE
MATERIAL.
STYLE 6:
PIN 1. BASE
2. EMITTER
3. COLLECTOR
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without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
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including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
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