Order Number: 290645, Revi sion: 023
May 2005
Intel® Advanced+ Boot Block Flash
Memory (C3)
28F800C3, 28F160C3, 28F320C3 (x16)
Datasheet
Product Featu res
The I nte l® Advanced+ Book Block Fl ash Mem ory (C3) device, manufactured on Intel ’s la tes t
0.13 µm and 0.18 µm technologies, repre sents a feature-rich sol ution for low-power
applicati ons. The C3 devic e incorporat es low-volt age capability (3 V read, program, and erase)
with high-speed, low-power operation. Flexible block locking allows any block to be
independently locke d or unlocked. Add to this the Intel® Flash Data I ntegrator (Int el® FDI )
software and you have a cost-effective, fl exible, monolithic code plus data storage solution.
Intel® Advanced+ Boot Block Flash Memor y (C3) products are ava ilable in 48-lead TSOP, 48-
ball CSP, and 64-ball Easy BGA pa ckages. Additional information on this product fa mily can be
ob tained f r om the Int el® Flash website: http://www.intel.com/design/flash.
■Fle xib le SmartVoltag e Technology
—2.7 V– 3.6 V read/program/erase
—12 V for fast production programming
■1.65 V to 2.5 V or 2.7 V to 3.6 V I/O
Option
—Reduc es overall system power
■High Performance
—2.7 V– 3.6 V: 70 ns max access time
■Optimized Architecture for Code Plus
Data Storage
—Eight 4 Kword blocks, top or bottom
parameter boot
—Up to 127 x 32 Kword blocks
—Fas t program suspend capability
—F as t er ase su sp en d cap ab i li ty
■Flexible Block Lockin g
—Lock/unlock any block
—Full protection on power-up
—Write Protect (WP#) pin for hardware
block protection
■Low Power Consum ption
—9 mA ty p i cal read
—7 uA typ ica l standby with Autom atic
Power Savings fea ture
■Extended Temperature Operation
—-40 °C to +85 °C
■128-bit Protection Register
—64 bit unique device identifier
—64 bit us er programmable OTP cells
■Extended Cycling Capability
—Minimu m 100, 000 block erase cycl es
■Software
—Supported by Intel’s Advanced Flash
File Manager s -- Int el® VFM, Intel®
FDI, etc.
—Code and da ta sto r age in the same
memory device
—Robust Power Loss Recove ry for Data
Loss Prevention
—Common Flash Interface
—http://www.intel.com/go/flashsw
■Standard Surface Mount Packaging
—48-Ball µBGA*/VFBGA
—64-Ball Easy BGA packages
—48-TSOP package
■ETOX™ VIII (0.13 µm) Fla sh
Technology
—8, 16, 32 Mbit
■ETOX™ VII (0.18 µm) Flash Technology
—16, 32 Mbit
■ETO X ™ VI (0.25 µm) Flash Technol ogy
—8, 16 and 32 Mbit
May 2005 Intel® Advanced+ Bo ot Block Flash Memory (C3) Datasheet
2 Order Numbe r: 290645 , Revision: 023
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Copyright © 2005, Intel Corporation. All Rights Reserved.
Intel® Advanced+ Boot Bloc k Flash Memory (C3)
Datasheet I ntel® Advanced+ B oot Block Flash Mem ory (C3) May 20 05
Order Number: 290645, Revisio n: 023 3
Contents
1.0 Introduction....................................................................................................................................7
1.1 Nomenclature .......................................................................................................................7
1.2 Conventions..........................................................................................................................7
2.0 Function al Overvi ew .....................................................................................................................8
2.1 Pro duct Overview .................................................................................................................8
2.2 Block Diagram ............ ..... ......... ..... .......... .... ..... .......... .... .......... ..... ......... ..... ......... ..... ...........9
2.3 Memory Map.........................................................................................................................9
3.0 Package Information ...................................................................................................................12
3.1 mBGA * and VF BGA Packa g e..... ..... .... ..... .......... .... .......... .... ..... .......... .... ..... .......... .... .......12
3.2 TSOP Package...................................................................................................................13
3.3 Easy BGA Package............................................................................................................14
4.0 Ballout and Signal Descriptions ................................................................................................15
4.1 48-Lead TSOP Package................ .............. ............ ....... ....... ................. ......... ............ .......15
4.2 64-Ball Easy BGA Package................................................................................................18
4.3 Signal Descriptions... .. ............ ............ ....... ............ ......... ....... ............ ....... ....... ............ .......18
5.0 Maximum Ratings and Operating Conditions...........................................................................20
5.1 Absolute Maxi mu m Ratings........... .......... .... .......... ..... ......... ..... ......... ..... ......... ..... .......... ....20
5.2 Ope r at i n g Condi tions..... .... ..... .......... .... .......... ..... .... .......... .... .......... ..... ......... ..... ..... ......... ..20
6.0 Electrical Specifications .............................................................................................................22
6.1 Curr e n t Ch ar ac te r istics.... ..... .... .......... ..... ......... ..... ......... ..... ..... ......... ..... ......... ..... ..... .........22
6.2 DC Volt a ge Characteristics............ ..... ......... ..... .......... .... .......... ..... .... .......... .... .......... ..... ....24
7.0 AC Characteristics ......................................................................................................................25
7.1 AC Read Characteri sti c s ... .......... ..... ......... ..... ......... ..... ......... ..... .......... ......... ..... ......... ..... ..25
7.2 AC Writ e Chara cte r i stic s....... ......... ..... ......... ..... .......... .... .......... ..... ......... ..... ......... ..... .........29
7.3 Er as e an d Prog ra m Ti mi n g s..... .......... ..... ......... ..... ..... ......... ..... ......... ..... ..... ......... ..... .........33
7.4 AC I/O Test Conditions........... .. .......... .. ....... ..... ..... ....... .. ....... ..... ....... ..... .. ....... ..... ....... ..... ..33
7.5 Device Capacitanc e. ............................... ................................. .......................... .................34
8.0 Power and Reset Specifications ................................................................................................35
8.1 Active Power (Program/Erase/Read)............................................ .............. ........................35
8.2 Automatic Power Savings (APS) ........................................................................................35
8.3 Sta n dby Po we r .... ..... ..... ......... ..... ..... ......... ..... ......... ..... ......... ..... ..... ......... ..... .......... .... .......35
8.4 Deep Power-Down Mode..................................................................... .............. .................35
8.5 Power and Res et Considerat ions................ ..... .......... .... .......... ..... ......... ..... ......... ..... ..... ....36
8.5.1 Power -U p /Down Characteristics... ..... ......... ..... ......... ..... ..... ......... ..... .......... .... .......36
8.5.2 RP# Connected to System Reset............. ....... .. ....... .......... ....... ....... ....... ....... .......36
8.5.3 VCC, VPP and RP# Transitions ....... ................... ..................................................36
8.5.4 Rese t Sp e cifications............ .... .......... ..... .... .......... .... .......... ..... .... .......... ..... ......... ..37
8.6 Power Su p ply De co upl ing....... .......... .... .......... ..... .... .......... .... .......... ..... ......... ..... ..... ......... ..37
9.0 Device Ope rations.......................................................................................................................39
Intel® Advanced + Boot Block Flash Memo ry (C3 )
May 2005 Intel® Advanced+ Bo ot Block Flash Memory (C3) Datasheet
4 Order Numbe r: 290645 , Revision: 023
9.1 Bus Operations...................................................................................................................39
9.1.1 Read......................................................................................................................39
9.1.2 Write ......................................................................................................................39
9.1.3 Output Disable.......................................................................................................39
9.1.4 Standby..................................................................................................................40
9.1.5 Reset .....................................................................................................................40
10.0 Mo des of Op erati on.....................................................................................................................41
10.1 Read Mode.........................................................................................................................41
10.1.1 R ead Array.............................................................................................................41
10.1.2 R ead Iden tifier .............................. ............................................. ............................41
10.1 .3 CFI Query..... ......... ..... ......... ..... ..... ......... ..... ......... ..... ..... ......... ..... ......... ..... ..... ......42
10.1.4 R ead Status Register........ ........................ ..................... ................... .....................42
10.1.4.1 Clear Status R egister.............................................................................43
10.2 Program Mode....................................................................................................................43
10.2.1 1 2-Volt Production Prog ramming . . ................... .......................... ................... .........43
10.2.2 Suspending and Resum ing Program...................... .......................... .....................44
10.3 Erase Mode........................................................................................................................44
10.3.1 Suspending and Resum ing Eras e....... ............................... .............................. .....45
11.0 Security Modes............................................................................................................................49
11.1 Flexible Block Locki n g. ..... ......... ..... ......... ..... ..... ......... ..... ......... ..... .......... .... ..... .......... .... . ...49
11.1.1 Locking Operation..................................................................................................50
11.1.1.1 Locked State..........................................................................................50
11.1.1.2 Unlocked State.......................................................................................50
11.1.1.3 Lock-Down State....................................................................................50
11.2 Reading Block-Lock Status... ................... ................... .............. ............ .............. ................50
11.3 Locking Operations during Erase Suspend........................................................................51
11.4 Status Register Error Checking..........................................................................................51
11.5 128-Bit Protection Register.................................................................................................51
11.5.1 R eading the Protection Register... .......................... ................................. ..............52
11.5 .2 Prog ra mmi n g the Pro te ction Regi ster........ .... .......... .... .......... ..... .... .......... ..... ........52
11.5.3 Locking the Protection Register .............................................................................52
11.6 VPP Program and Erase Voltages .................. ................. ......... ............ .............. ............ ....52
11.6.1 Program Protection................................................................................................53
A W rite State Machine S tates.........................................................................................................54
BFlow Charts..................................................................................................................................56
C Co m m on Flash I nter fac e.............................................................................................................62
C.1 Query Stru cture Outpu t.. ..... ......... ..... ..... ......... ..... .......... .... .......... ..... .... .......... .... .......... ......62
C.2 Query Stru cture Overview.... ..... .......... .... ..... .......... .... .......... .... .......... ..... ......... ..... ..... ........63
C.3 Block Status Register.........................................................................................................64
C.4 CFI Query Identification String................. ....... ............ ....... ....... .......... ....... ......... .......... ......65
C.5 Device Geo metry Definitio n..... .... .......... ..... ......... ..... ......... ..... ..... ......... ..... ......... ..... .......... .66
C .6 Int el-Spec ific Extended Query Table............................ ................................. .....................68
D Additional Information................................................................................................................70
E O r d ering Inf o r m ati on...................................................................................................................71
Intel® Advanced+ Boot Bloc k Flash Memory (C3)
Datasheet I ntel® Advanced+ B oot Block Flash Mem ory (C3) May 20 05
Order Number: 290645, Revisio n: 023 5
Revision History
Date of
Revision Version Description
05/12/98 -001 Origi nal ve rsion
07/21/98 -002
48-Lead TSOP package diagram change
µBGA package diagrams change
32-Mbit ordering information change (Section 6)
CFI Q uery Struct ure Ou tput Tabl e Change (Table C2)
CFI Primary- Vendor Spec ific Extende d Q uery Table Change f or Op tional Features an d
Command Support change (Table C8)
Protection Register Address Cha nge
IPPD test conditions clarification (Section 4.3)
µBGA package top side mark inf ormation cla rification (Section 6)
10/03/98 -003
Byte-W ide Protection Register Address change
VIH Specificat ion c hange (Section 4.3)
VIL Maximum Specification change (Section 4.3)
ICCS test conditions clarification (Section 4.3)
Added Command Sequence Error Note (Table 7)
Datasheet renamed from 3 Volt Advanced Boot Block, 8-, 16-, 32-Mbit Flash Memory
Family.
12/04/98 -004 Ad de d tBHWH/tBHEH and tQVBL (Section 4.6)
Programming the Protection Register clarification (Section 3.4.2)
12/31/98 -005 Removed all references to x8 configurations
02/24/99 -006 Removed reference to 40-Lead TSOP from front page
06/10/99 -007
Added Easy BGA package (Section 1.2)
Removed 1.8 V I/O references
Locking Operation s Flowchart changed (Appendix B)
Ad de d tWHGL (Section 4.6)
CFI Primary Vendor-Specific Extended Query changed (A ppen dix C)
03/20/00 -008 Max ICCD chan ge d to 25 µ A
Table 10, added note indicating VCCMax = 3. 3 V for 32-Mbit device
04/24/00 -009 Added speci fications for 0.18 micron pro duct offer ing s throughout document Added 64-
Mbit density
10/12/00 -010
Changed references of 32Mbit 80ns devices to 70ns devices to reflect the faster product
offering.
Changed VccMax =3.3V refere nce to indi cate that the affected product is the 0.25 µm
32Mbit devi ce.
Minor text edits throughout document.
7/20/01 -011
Added 1.8v I/O ope ration documentation whe re appli cable
Added TSOP PCN ‘Pin-1’ indicator inf orma tio n
Changed references in 8 x 8 BGA pinout diagrams from ‘GND’ to ‘Vssq’
Added ‘Vssq’ to Pin Descriptions Information
Removed 0.4 µm references in DC characteristics table
Cor rected 64Mb p ackage Or dering Information from 48-uBGA to 48-VFB GA
Corrected ‘bottom’ parameter bloc k size s to on 8Mb device to 8 x 4KWords
Minor text edits throughout document
10/02/01 -012 Added specifications for 0.13 micron pro duct offerings through out docume nt
2/05/02 -013 Corrected Iccw / Ippw / Icces /Ippes values.
Added mechanicals for 16Mb and 64Mb
Minor text edits throughout document.
Intel® Advanced + Boot Block Flash Memo ry (C3 )
May 2005 Intel® Advanced+ Bo ot Block Flash Memory (C3) Datasheet
6 Order Numbe r: 290645 , Revision: 023
4/05/02 -014
Updated 64Mb product offer ing s.
Updated 16Mb product offer ing s.
Revised and corre cted DC Charact eristics Tabl e.
Added mechanicals for Easy BGA.
Minor text edits throughout document.
3/0 6/ 03 -01 6 Com p le t e tec h nic a l update.
10/01/03 -017 Corrected information in the Device Geometry Details table, address 0x34.
5/2 0/ 04 -01 8 Upd ated the lay o ut of th e data sheet .
9/1/04 -019 Fixed typo for Stan dby po wer on cover page.
9/14 /04 -020 Added lead -free line items to Tabl e 37 “Product Information Orde ring Matrix” on page 72.
9/27/04 -021 Added specification for 8Mb 0.13 micron devic e.
Added 0.13 micron to Table 37 “Product Information Ordering Matrix” on page 72.
1/26/05 -022 C on v er te d da t as he et to new tem pl at e . D el ete d D es c ript io n in Table 4. D el et e d Note in
Figure 5.
5/16/05 -023
Removed all 64M ordering information, removed VF BGA 8M ordering information.
Re mov ed 64M r e fer en ce in ti tl e page o nl y. Adde d s of tw a re v erbi a ge in tit l e p a ge. Cor r ect ed
Lead Width (b) measur ement in Fig 2., uBGA and VF BGA Pa ckage Drawing and
Dimensions, page 12.
Date of
Revision Version Description
Intel® Advanced+ Boot Bloc k Flash Memory (C3)
Datasheet I ntel® Advanced+ B oot Block Flash Mem ory (C3) May 20 05
Order Number: 290645, Revisio n: 023 7
1.0 Introduction
This datas heet contains the specif ica tions for th e I n tel® A dvanced+ Boot Block Flash Memory
(C3) device family, hereafter called the C3 flash memory device. These flash memories add
features such as in st ant block locking and prot ection registers tha t can be used to enhance the
se curity of system s.
1.1 Nomenclature
0x Hexade cimal prefix
0b Binary prefix
Byte 8 bits
Word 16 bi ts
KW or Kword 1024 words
Mword 1,048, 576 words
Kb 1024 bits
KB 1024 bytes
Mb 1,048,576 bits
MB 1,048,576 bytes
APS Aut omatic Power Savings
CSP Chip Scale Pac k age
CUI Command User Interface
OTP On e Time Progra mma ble
PR Protection Register
PRD Protection Register Data
PLR Protection Lock Register
RFU Res erved for Future Use
SR Status Register
SRD Status Register Data
WSM Writ e St at e M ach i n e
1.2 Conventions
The terms pin and signal are often us ed interc hangeably t o refer to the external signal connections
on the pa ck ag e ; f or ch ip scal e pa ck age (C S P) th e te r m ball is u s e d.
Group Membership Brackets: S quare brackets will be used to designate group m em bership or to
define a group of signals wit h si mi lar funct ion (i.e. A[21:1], SR[4:1])
Set: When referring to registers , the term set mea ns the bit is a logical 1.
Clear: When referrin g to registers, the term clear means the bit is a logica l 0.
Block: A group of bits (or words ) that erase simultaneously with one block erase instruction.
Main Block: A block that c ontains 32 Kwords.
Para meter Block: A block tha t contains 4 Kwords.
Intel® Advanced + Boot Block Flash Memo ry (C3 )
May 2005 Intel® Advanced+ Bo ot Block Flash Memory (C3) Datasheet
8 Order Numbe r: 290645 , Revision: 023
2.0 Functional Overview
Thi s secti on provide s an over view of the In tel® Adva nced+ Boot Block Flash Memory (C3 ) devi ce
feat u r es an d ar chite ct u re .
2.1 Product Overview
The C3 flash mem ory device provides high-performance asynchronous rea ds in package-
compatible densities with a 16 bit data bus. Individually-erasable memory blocks are optimally
sized for code and data s torage. Eight 4 Kword paramet er blocks are located in the boot block at
either the top or bottom of the device’s memory map. The rest of the memory array is grouped into
32 Kword main blocks.
The device supports rea d-array mode operations at various I/O voltages (1.8 V and 3 V) and erase
and program operati ons at 3 V or 12 V VPP. With the 3 V I/O option , VCC and VPP can be tied
together for a simp le, ultra-low-power design. In addition to I/O volt age flexibility, the dedica ted
VPP input provides complete dat a protecti on when VPP ≤ VPPLK.
The Intel® Advanced+ Boot Block Flas h Mem ory (C3) device fe atures a 128-bit protection
register enabling security techniques and data protection schemes through a combination of
factory-programmed and user-program mable OTP data registers. Zero-latency locking/unlocking
on any mem ory block provides instant and complete protection for critical system code and data.
Additional block loc k-down capabi lity provides hardware protection where software commands
alone cannot change the block’s protection status .
A c omma nd Use r In t erfa ce (CUI) ser v es as th e int erf ac e be twe en th e sys te m pro ce ssor a nd in ternal
operation of the device. A valid command sequence is sued to the CUI initiates device aut omation.
An in ternal Write St ate Machine (WSM) automatic ally execut es th e algor ithm s and timing s
necessary for block erase, program, and lock-bit configuration operations.
The device offers three low-power saving fea tures: Auto matic Power Savings (APS), st andby
mode , a nd dee p power-d own mode. The devic e aut om atically enters APS mode following rea d
cycle completion. Standby mod e begins when the sy st em des elects the flash memory by
deasserting Chip Enable, CE#. The deep power- down mode begins when Re se t Deep Power-
Down , RP# is asserted, which deselects the memory a nd places the outputs in a high-im pedance
state, producing ultra-low power savings. Combined, these three power-savings features
significa ntly enhanc ed power consum ption flexibility.
Intel® Advanced+ Boot Bloc k Flash Memory (C3)
Datasheet I ntel® Advanced+ B oot Block Flash Mem ory (C3) May 20 05
Order Number: 290645, Revisio n: 023 9
2.2 Block Diagram
2 .3 Mem or y Ma p
The Int el® Advanced+ Boot Block Fl as h Memory (C3) device is asymm etrically blocke d, which
enables system code and data integration within a singl e fla sh device. The bulk of the array is
divided into 32 Kword main blocks that can store code or data, and 4 Kword boot blocks to
faci litate st orage of boot code or for freque ntly chang ing small parameters. S ee Table 1, “Top Boot
Memory Map” on page 10 an d Table 2, “Bottom Boot Memory Map” on page 11 for det ails.
Figure 1. C3 Flash Memory Device Block Diagram
Output
M ultiplexer
4-KWord
Pa rameter Block
32- KWord
Main Block
32- KWord
Main Block
4-KWord
Pa rameter Block
Y-Gating/Sensing Wr it e S tate
Machine Program/Erase
V ol t ag e Sw it c h
Data
Comparator
Status
Register
Identifier
Register
Data
Register
I/O L ogi c
Address
Latch
Address
Counter
X-Decoder
Y-Decoder
Power
Reduction
Control
Input Buf fer
Output Buffer
GND
V
CC
V
P
P
CE#
WE#
OE#
RP#
Command
User
Interface
Input Buff er
DQ
0
-DQ
15
V
CCQ
WP#
A
[MAX:MIN]
Intel® Advanced + Boot Block Flash Memo ry (C3 )
May 2005 Intel® Advanced+ Bo ot Block Flash Memory (C3) Datasheet
10 Order Numbe r: 290645 , Revision: 023
Ta b le 1. Top B oot M emory Map
Size
(KW) Blk 8-Mbit
Memory
Addressing
(Hex)
Size
(KW) Blk 16-Mbit
Memory
Addressing
(Hex)
Size
(KW) Blk 32-Mbit
Memory
Addressing
(Hex)
Size
(KW) Blk 64- Mbit Memo ry
Addressing (Hex)
422 7F000-
7FFFF 4 38 FF000-FFFFF 470 1FF000-
1FFFFF 4 134 3FF000-3FFFFF
421 7E000-
7EFFF 4 37 FE000-FEFFF 4691FE000-
1FEFFF 4 133 3FE000-3FEFFF
420 7D000-
7DFFF 4 36 FD000-FDFFF 4681FD000-
1FDFFF 4 132 3FD000-3FDFFF
419 7C000-
7CFFF 4 35 FC000-FCFFF 4671FC000-
1FCFFF 4 131 3FC000-3FCFFF
418 7B000-
7BFFF 4 34 FB000-FBFFF 4661FB000-
1FBFFF 4 130 3FB000-3FBFFF
417 7A000-
7AFFF 4 33 FA000-FAFFF 465 1FA000-
1FAFFF 4 129 3FA000-3FAFFF
4 16 79000-79FFF 4 32 F9000-F9FFF 464 1F9000-
1F9FFF 4 128 3F9000-3F9FFF
4 15 78000-78FFF 4 31 F8000-F8FFF 463 1F8000-
1F8FFF 4 127 3F8000-3F8FFF
32 14 70000-77FFF 32 30 F0000-F7FFF 32 62 1F0000-
1F7FFF 32 126 3F0000-3F7FFF
32 13 68000-6FFFF 32 29 E8000-EFFFF 32 61 1E8000-
1EFFFF 32 125 3E8000-3EFFFF
32 12 60000-67FFF 32 28 E0000-E7FFF 32 60 1E0000-
1E7FFF 32 124 3E0000-3E7FFF
32 11 58000-5FFFF 32 27 D8000-DFFFF 32 59 1D8000-
1DFFFF 32 123 3D8000-3DFFFF
... ... ... ... ... ... ... ... ... ... ... ...
32 2 10000-17FFF 32 2 10000-17FFF 32 2 10000-17FFF 32 2 10000-17FFF
32 1 8000-0FFFF 32 1 08000-0FFFF 32 1 08000-0FFFF 32 1 08000-0FFFF
32 0 0000-07FFF 32 0 00000-07FFF 32 0 00000-07FFF 32 0 00000-07FFF
Intel® Advanced+ Boot Bloc k Flash Memory (C3)
Datasheet I ntel® Advanced+ B oot Block Flash Mem ory (C3) May 20 05
Order Number: 290645, Revisio n: 023 11
Table 2. Bottom Boot Memory Map
Size
(KW) Blk 8-Mbit
Memory
Addressing
(Hex)
Size
(KW) Blk 16-Mbit
Memory
Addressing
(Hex)
Size
(KW) Blk 32-Mbit
Memory
Addressing
(Hex)
Size
(KW) Blk 64-Mbit Memory
Addressing (Hex)
32 22 78000-7FFFF 32 38 F8000-FFFFF 32 70 1F8000-1FFFFF 32 134 3F8000-3FFFFF
32 21 70000-77FFF 32 37 F0000-F7FFF 32 69 1F0000-1F7FFF 32 133 3F0000-3F7FFF
32 20 68000-6FFFF 32 36 E8000-EFFFF 32 68 1E8000-1EFFFF 32 132 3E8000-3EFFFF
32 19 60000-67FFF 32 35 E0000-E7FFF 32 67 1E0000-1E7FFF 32 131 3E0000-3E7FFF
... ... ... ... ... ... ... ... ... . ... ...
32 10 18000-1FFFF 32 10 18000-1FFFF 32 10 18000-1FFFF 32 10 18000-1FFFF
32 9 10000-17FFF 32 9 10000-17FFF 32 9 10000-17FFF 32 9 10000-17FFF
32 8 08000-0FFFF 32 8 08000-0FFFF 32 8 08000-0FFFF 32 8 08000-0FFFF
4 7 07000-07FFF 4 7 07000-07FFF 4 7 07000-07FFF 4 7 07000-07FFF
4 6 06000-06FFF 4 6 06000-06FFF 4 6 06000-06FFF 4 6 06000-06FFF
4 5 05000-05FFF 4 5 05000-05FFF 4 5 05000-05FFF 4 5 05000-05FFF
4 4 04000-04FFF 4 4 04000-04FFF 4 4 04000-04FFF 4 4 04000-04FFF
4 3 03000-03FFF 4 3 03000-03FFF 4 3 03000-03FFF 4 3 03000-03FFF
4 2 02000-02FFF 4 2 02000-02FFF 4 2 02000-02FFF 4 2 02000-02FFF
4 1 01000-01FFF 4 1 01000-01FFF 4 1 01000-01FFF 4 1 01000-01FFF
4 0 00000-00FFF 4 0 00000-00FFF 4 0 00000-00FFF 4 0 00000-00FFF
Intel® Advanced + Boot Block Flash Memo ry (C3 )
May 2005 Intel® Advanced+ Bo ot Block Flash Memory (C3) Datasheet
12 Order Numbe r: 290645 , Revision: 023
3.0 Package Information
3.1 µBGA* and VF BGA Pac kage
Figu re 2. µBGA* and VF BGA Package Drawing and Dimensions
Bottom View -Bump side up
e
b
S1
Ball A1
Corner
T op V iew -Bum p S ide down
Ball A 1
Corner
E
D
Side View
A
A2
A
1
Seating
Y
A
B
C
D
E
F
S2
Plan
123
4
5678
A
B
C
D
E
F
123
4
5678
Not e: Drawing not t o scale
Millimeters Inches
Dimensions Symbol Min Nom Max Min Nom Max
Package Height A 1.000 0.0394
Ball Height A1 0.150 0.0059
Package Body T hick ness A2 0.665 0.0262
Ball (Lead) Width b 0.325 0.375 0.425 0.0128 0.0148 0.0167
Package Body Length 8M (.25) D 7.810 7 .910 8.010
Package Body Length 16M (.25/.18/.1 3) 32M (.25/. 18/.13) D 7.186 7 .286 7.386 0.2829 0 .2868 0.290 8
Package Body Length 64M (.1 8) D 7.600 7 .700 7.800 0.2992 0.3031 0.3071
Package Body Width 8M (.25) E 6.400 6.500 6.600 0.2520 0.2559 0.2598
Package Body Width 1 6M (.25/.18/.13) 32M (.18/. 13) E 6.864 6.9 64 7.064 0.2702 0.2 742 0.278 1
Package Body Width 32M (.25) E 10.7 50 10.850 10.860 0.4232 0 .4272 0.4276
Package Body Width 64M (.18) E 8.900 9.000 9.100 0.3504 0.3543 0.3583
Pitch e 0.750 0.0295
Ball (Lead) Count 8M, 16M N 46 46
B al l (L ea d) Count 32 M N 47 47
B al l (L ea d) Count 64 M N 48 48
Seating Plane Coplanarity Y 0.100 0.0039
Corner to Ball A1 Distance Along D 8M (.25) S1 1.230 1 .330 1.430 0.0484 0.0524 0.0563
Corner to Ball A1 Distance Along D 1 6M (.25/.18/.13) 32M (.18/.13) S1 0.918 1.018 1.118 0.0361 0.0401 0.0440
Corner to Ball A1 Distance Along D 64M (.18) S1 1.125 1 .225 1.325 0.0443 0.0482 0.0522
Corner to Ball A1 Distance Along E 8M (.25) S2 1.275 1.375 1.475 0.0502 0.0541 0.0581
Corner to Ball A1 Distance Along E 16M (.25/.1 8/.13) 32M (.18/.13) S2 1.507 1.607 1.707 0.0593 0.0633 0.0672
Corner to Ball A1 Distance Along E 32M (.25) S2 3.450 3 .550 3.650 0.1358 0.1398 0.1437
Corner to Ball A1 Distance Along E 64M (.18) S2 2.525 2 .625 2.725 0.0994 0.1033 0.1073
C3 Discrete 8/ 16/32/64M,
.25,.18, .13u ubga/VFBGA
R0
Intel® Advanced+ Boot Bloc k Flash Memory (C3)
Datasheet I ntel® Advanced+ B oot Block Flash Mem ory (C3) M ay 2005
Order Number: 290645, Revisio n: 023 13
3.2 TSOP Package
Notes:
1. One dimple on package denotes Pin 1.
2. If two dimples, then the larger dimple denotes Pin 1.
3. Pin 1 will always be in the upper left corner of the package, in reference to the product mark.
Figure 3. TSO P Packag e Drawing and Dimensi ons
Dimensions
A5568-02
A
0
L
Det ail A
Y
D
C
Z
Pin 1
E
D
1
b
Detail B
S ee D eta il A
e
See Detail B
A
1
A
2
Seat ing
Plane
See Not es 1, 2, 3 and 4
Family: Thin Small Out-Li ne Package
Symbol Millimeters Inches
Min Nom Max Notes Min Nom Max Notes
Package Height A 1.200 0. 047
Standoff A1 0.050 0.002
Package Body Thic knes s A2 0.950 1.000 1.050 0.037 0. 039 0.041
Lead Width b 0.150 0. 200 0.300 0. 006 0.008 0.012
Lea d Thi c k n es s c 0 . 100 0. 1 50 0. 200 0.0 04 0. 00 6 0.008
Plast ic Body Lengt h D 1 18. 200 18.400 18. 600 0. 717 0.724 0.732
Package Body W idt h E 11.800 12. 000 12. 200 0.465 0. 472 0. 480
Lead Pitc h e 0.500 0.0197
Term inal Dimens ion D 19.800 20. 000 20.200 0.780 0.787 0.795
Lead T ip Length L 0.500 0.600 0. 700 0. 020 0.024 0.028
Lead Count N 48 48
Lead Tip Angle Ø 0° 3° 5° 0° 3° 5°
Seating Plane Coplanarit y Y 0.100 0.004
Lead to Pack age Off s et Z 0.150 0. 250 0. 350 0.006 0.010 0. 014
Intel® Advanced + Boot Block Flash Memo ry (C3 )
May 2005 Intel® Advanced+ Bo ot Block Flash Memory (C3) Datasheet
14 Order Numbe r: 290645 , Revision: 023
3.3 Easy BGA Package
Figure 4. Easy BGA Package Drawing an d Dimension
Millimeters Inches
Symbol Min Nom Max
Notes
Min Nom Max
Package Height A 1.200 0.0472
Ball Height A10.250 0.0098
Package Body Thickness A20.780 0.0307
Ball (Lead) Width b 0.330 0.430 0.530 0.0130 0.0169 0.0209
Package Body Width D 9.900 10.000 10.100 1 0.3898 0.3937 0.3976
Package Body Length E 12.900 13.000 13.100 1 0.5079 0.5118 0.5157
Pitch [e] 1.000 0.0394
Ball (Lead) C ount N 64 64
Seating Plane Coplanarity Y 0.100 0.0039
Corner to Ball A1 Distance Along D S11.400 1.500 1.600 1 0.0551 0.0591 0.0630
Corner to Ball A1 Distance Along E S22.900 3.000 3.100 1 0.1142 0.1181 0.1220
Dimensions Table
Note: (1) Package dimensions are for reference only. These dimensions are estimates based
on die size, and are subject to change.
E
Seating
Plane
S1
S2
e
Top View - Ball side down Bo ttom V ie w - Ball Si de Up
Y
A
A1
D
Ball A1
Corner
A2
Note: Drawing not to scale
A
B
C
D
E
F
G
H
8765432187654321
A
B
C
D
E
F
G
H
b
Ball A1
Corner
Side View
Intel® Advanced+ Boot Bloc k Flash Memory (C3)
Datasheet I ntel® Advanced+ B oot Block Flash Mem ory (C3) M ay 2005
Order Number: 290645, Revisio n: 023 15
4.0 Ballout and Signal Descriptions
The C3 device is available in 48- lead TSOP, 48-ball VF BGA, 48-ball µBGA, and Easy BGA
packages. See Figure 5 on page 15, Figure 7 on pag e 17, and F igure 8 on page 18, respectively.
4.1 48-Lead TSOP Package
Figure 5. 48-Lead TSO P Package
Advanced+ Boot Block
48-Lead TSOP
12 mm x 20 mm
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A
16
V
CCQ
GND
DQ
15
DQ
7
DQ
14
DQ
6
DQ
13
DQ
5
DQ
12
DQ
4
V
CC
DQ
11
DQ
3
DQ
10
DQ
2
DQ
9
DQ
1
DQ
8
DQ
0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
21
A
20
WE#
RP#
V
PP
WP#
A
19
A
18
A
17
A
7
A
6
A
5
21
22
23
24
OE#
GND
CE#
A
0
28
27
26
25
A
4
A
3
A
2
A
1
32 M
16 M
64 M
Intel® Advanced + Boot Block Flash Memo ry (C3 )
May 2005 Intel® Advanced+ Bo ot Block Flash Memory (C3) Datasheet
16 Order Numbe r: 290645 , Revision: 023
Figure 6. Mark for Pin-1 Indicator on 48-Lead 8-Mb, 16-Mb an d 32-Mb TSOP
Note: The topside marking on 8 Mb, 16 Mb, and 32 Mb Intel
®
Advanced and Advanced + Boot Block
48 L TSOP products will convert to a white ink triangle as a Pin 1 indic ator. Products without the
white triangle will cont inue to use a dimpl e as a Pin 1 ind icator. There are no other changes in
package size, m aterials, f unctionality, customer handling, or manufactura bility. Pr oduct will
continue to meet Intel stringent quality requirements. Products affected are Intel Ordering Codes
sh own in Table 3.
Table 3. 48-Lead TSOP
Extended 64 Mbit Extended 32 Mbit Extended 16 Mbit Extended
TE28F320C3TD70
TE28F320C3BD70 TE28F160C3TD70
TE28F160C3BD70 TE28F800C3TA90
TE28F800C3BA90
TE28F320C3TC70
TE28F320C3BC70 TE28F160C3TC80
TE28F160C3BC80 TE28F800C3TA110
TE28F800C3BA110
TE28F320C3TC90
TE28F320C3BC90 TE28F160C3TA90
TE28F160C3BA90
TE28F320C3TA100
TE28F320C3BA100 TE28F160C3TA110
TE28F160C3BA110
TE28F320C3TA110
TE28F320C3BA110
C
urrent Mark:
N
ew Ma rk:
Intel® Advanced+ Boot Bloc k Flash Memory (C3)
Datasheet I ntel® Advanced+ B oot Block Flash Mem ory (C3) M ay 2005
Order Number: 290645, Revisio n: 023 17
Notes:
1. Sha ded connec tions indicate t he up grade address connec tions. In tel re commends to no t use routin g in
this area.
2. A19 denotes 16 Mbit; A20 denotes 32 Mbit; A21 denotes 64 Mbit.
3. Unused address balls are not populated.
Figure 7. 48-Ball µBGA * and 48-Ball VF BGA Chip Scale Package (To p View, Ball Down)1,2,3
13254768
A
B
C
D
E
F
A13
A14
A15
A16
VCCQ
A11
A10
A12
D14
D15
A8
WE#
A9
D5
D6
VPP
RP#
A21
D11
D12
WP#
A18
A20
D2
D3
A19
A17
A6
D8
D9
A7
A5
A3
CE#
D0
A4
A2
A1
A0
GND
GND D7 D13 D4 VCC D10 D1 OE#
16M
32M64M
Intel® Advanced + Boot Block Flash Memo ry (C3 )
May 2005 Intel® Advanced+ Bo ot Block Flash Memory (C3) Datasheet
18 Order Numbe r: 290645 , Revision: 023
4.2 64-Ball Easy BGA Package
Figure 8. 64-Ball Easy BGA Packag e1,2
Notes:
1.A19 denotes 16 Mbit; A20 denotes 32 Mbit; A21 denotes 64 Mbit.
2. Unused address ba lls are not populated.
4.3 Sig nal Descriptions
1
2
3
4
5
6
7
8
A
B
C
D
E
F
G
H
Top View
- Ball Side
Down
Bottom View - Ball Side
Up
A
1
A
6
A
18
V
PP
V
CC
GND
A
10
A
15
A
2
A
17
A
19
(1)
RP#
DU
A
20
(1)
A
11
A
14
A
3
A
7
WP#
WE#
DU
A
21
(1)
A
12
A
13
A
4
A
5
DU
DQ
8
DQ
1
DQ
9
DQ
3
DQ
12
DQ
6
DU
DU
CE#
DQ
0
DQ
10
DQ
11
DQ
5
DQ
14
DU
DU
A
0
V
SSQ
DQ
2
DQ
4
DQ
13
DQ
15
VSSQ
A
16
A
22
(2)
OE#
V
CCQ
V
CC
V
SSQ
DQ
7
V
CCQ
DU
DU
DU
DU
A
8
A
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
A
15
A
10
GND
V
CC
V
PP
A
18
A
6
A
1
A
14
A
11
A
20
(1)
DU
RP#
A
19
(1)
A
17
A
2
A
13
A
12
A
21
(1)
DU
WE#
WP#
A
7
A
3
A
9
A
8
DU
DU
DU
DQ
6
DQ
12
DQ
3
DQ
9
DQ
1
DQ
8
DU
DU
DQ
14
DQ
5
DQ
11
DQ
10
DQ
0
CE#
A
16
VSSQ
D
15
D
13
DQ
4
DQ
2
V
SSQ
A
0
DU
V
CCQ
D
7
V
SSQ
V
CC
V
CCQ
OE#
A
22
(2)
DU
DU
DU
A
5
A
4
Table 4. Signal Descript ions
Symbol Type Description
A[MAX:0] Input
ADDRESS INPUTS for memory addresses. Address are internally latched during a program or erase
cycle.
8 Mbit: AMAX= A18
16 Mbit: AMAX = A19
32 Mbit: AMAX = A20
64 Mbit: AMAX = A21
DQ[15:0] Input/
Output
DATA INPUTS/OUTPUTS: Inputs data and commands during a write cycle; outputs data during read
cycles. Inputs commands to the Command User Interface when CE# and WE# are active. Data is
intern ally latched. The data pins float to tr i-state when the chip is de-selected or t he ou tputs are
disabled.
CE# Input CHIP ENABLE: Acti ve- low inpu t. A c tiva tes th e i nter nal co ntrol l ogic , in pu t buf fe rs, deco de rs a nd sens e
am plif iers . CE # i s acti ve low. C E# hi gh de- s elec ts t he m emo ry de vice and redu ces po w er co nsum pti on
to standby levels.
OE# Input OUTPUT ENABLE: Active-l ow inpu t. Enabl es the device’s outpu ts throu gh the data buffers durin g a
Read operation.
Intel® Advanced+ Boot Bloc k Flash Memory (C3)
Datasheet I ntel® Advanced+ B oot Block Flash Mem ory (C3) M ay 2005
Order Number: 290645, Revisio n: 023 19
RP# Input
RE SET/ DEEP PO WER -DO WN: Active-low input.
When RP# is at logic low , the device is in reset/deep power-down mode, which drives the outputs to
High-Z, resets the Write State Machine, and minimizes current levels (ICCD).
When RP# is at logic high, the device is in standard operation. When RP# transitions from logic-low to
logic-high, the device resets all blocks to locked and defaults to the read array mode.
WE# Input WRITE ENABLE: Ac tive -lo w i nput . WE # cont rol s wr ite s to th e de vic e. A dd res s a nd da t a ar e la tc hed o n
the r ising edge of the WE# pulse.
WP# Input
WRITE PROTECT: Active-low input.
When WP# is a logic low, th e lock -d own mechanism i s enab led and blocks marked lock-down cannot
be unlocked through software.
When WP# is logic high, the lock-dow n mechanism is disabled an d blocks previous ly locked - down are
now locked and ca n be un locked and locked throu gh software. Af ter WP# goes low, an y blocks
previously marked lock-down revert to the lock-down state.
See Section 11.0, “Security Mode s” on pa ge 49 fo r d etail s on block locking.
VPP Input/
Power
P ROGR AM/ ERA SE Power Supply : Operates as an input at logic levels to control complete device
protection. Supplies power for accelerated Program and Erase operations in 12 V ± 5% range. Do not
leave this pin floating.
Lower VPP ≤ VPPLK to protect all contents against Program and Erase commands.
Set VPP = VCC for in-system Read, Program and Erase operations. In this configuration, VPP can
drop as low as 1.65 V to allow for resistor or diode drop from the system supply.
Apply VPP to 12 V ± 5 % for fas ter pro gra m an d e rase in a p r oduc ti on en vi ron men t. App l ying 1 2 V ± 5%
to VPP can only be done for a maximum of 1000 cyc les on the main blocks an d 2500 cycle s on the
boot blocks. VP P can be con nected to 12 V for a total of 80 hours m aximum. See Se c tio n 11 .6 for
deta il s on VPP volta ge conf ig ura ti on s.
VCC Power DEVICE CORE Power Supply: Supplies power for device operations.
VCCQ Power OUTPUT Power Supply: O utput -driven sou rce voltage. T his ball can be tied directly to VCC if
operating within VCC range.
GND Power Ground: For al l internal circuitry. A ll ground inputs must be connec ted.
DU — Do Not Use: Do not us e this bal l . This ball m u st not be connec t e d t o an y pow er su pplies, signals or
other balls,; it must be left floating.
NC — No Connect
Table 4. Signal Descriptions
Symbol Type Description
Intel® Advanced + Boot Block Flash Memo ry (C3 )
May 2005 Intel® Advanced+ Bo ot Block Flash Memory (C3) Datasheet
20 Order Numbe r: 290645 , Revision: 023
5. 0 Maxim um Rat ings and Ope r a t ing Condi tions
5.1 Absolute Maximum Ratings
Warning: Stressing the device beyo nd the “Absolut e Max im um Ra tings” may caus e pe rma nent damage.
The se ratings are stress rat ings only. Operation bey ond the “Operating Cond itions” is not
r ec ommended, and exte nded expos ure beyond the “Operating Conditions ” may affect devi ce
reliability.
.
5.2 Operating Cond itions
NOTICE: Specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest
datasheet before finalizing a design.
Parameter Maximum Rating Notes
Extended Operat ing Temperature
Dur ing Read –40 °C to +85 °C
During Block Erase and Program –40 °C to +85 °C
Temperature under Bias –40 °C to +85 °C
Stor age Temper ature –65 °C to +125 °C
Voltage On Any Pin (except VCC and VPP) with Respect to GND –0.5 V to +3.7 V 1
VPP Voltage (fo r Bloc k Erase and Pr ogram) w ith Re spect to GND –0.5 V to +13.5 V 1, 2,3
VCC an d VCCQ Supply V oltage with Respect to GND –0.2 V to +3.6 V
Out put Short Circu it Current 100 m A 4
Notes:
1.Minimum DC voltage is –0.5 V on input/output pins. During transitions, this level may
undershoot to –2.0 V for periods <20 ns . Maxim um DC vo ltage on input/ output pins is VCC
+0.5 V which, duri ng tra nsitions, may oversho ot to VCC +2.0 V for periods <20 ns.
2.Maxim um DC vo ltage on VPP may overshoot to +14.0 V for periods <20 ns.
3.VPP Program v oltage is n ormally 1.65 V–3.6 V. Connection to a 11.4 V –12 .6 V supp ly ca n be
done for a m aximu m of 1000 cycles on the main blocks an d 2500 c ycles on the parameter
bloc ks d uri ng pro gram /e ras e. VPP may be co nn ecte d t o 12 V for a tot al of 80 ho urs max imu m.
4.Output shorted for no more than one second. No more than one output shorted at a time.
Table 5. Tem p eratur e and Volta ge Op erating Co nditions
Symbol Parameter Notes Min Max Units
TAOperating Temperature –40 +85 °C
VCC1 VCC Supply Voltage 1, 2 2.7 3.6 Volts
VCC2 1, 2 3.0 3.6
VCCQ1
I/O Supply Voltage
12.73.6
VoltsVCCQ2 1.65 2.5
VCCQ3 1.8 2.5
VPP1 Supply Voltage 1 1.65 3. 6 Volts
Intel® Advanced+ Boot Bloc k Flash Memory (C3)
Datasheet I ntel® Advanced+ B oot Block Flash Mem ory (C3) M ay 2005
Order Number: 290645, Revisio n: 023 21
VPP2 1, 3 11.4 12.6 Vo lts
Cyclin g Block Er ase Cyclin g 3 100, 000 Cycl es
Notes:
1.VCC and VCCQ m ust share t he sam e supp ly when th ey are in the VCC1 ra nge.
2.VCCMax = 3.3 V for 0.25µm 32-Mbit devices.
3.Ap plying VPP = 1 1.4 V–12.6 V during a program/erase can only be done for a maximum of 1000 cycles on
the ma in block s and 25 00 cycles on the par amet er blocks. V PP may be connected to 12 V for a total of
80 hours maximum.
Table 5. Temperature and Voltag e Operating Conditions
Symbol Parameter Notes Min Max Units
Intel® Advanced + Boot Block Flash Memo ry (C3 )
May 2005 Intel® Advanced+ Bo ot Block Flash Memory (C3) Datasheet
22 Order Numbe r: 290645 , Revision: 023
6.0 Electrical Specifications
6.1 Current Characteristics
Table 6. DC Current Characteristics (Sheet 1 of 2)
Sym Parameter
VCC 2.7 V–3.6 V 2.7 V–2.85 V 2.7 V–3.3 V
Unit Test ConditionsVCCQ 2.7 V–3.6 V 1.65 V–2.5 V 1.8 V–2.5 V
Note Typ Max Typ Max Typ Max
ILI Input Load Current 1,2 ± 1 ± 1 ± 1µA
VCC = VCCMax
VCCQ = VCCQMax
VIN = VCCQ or GND
ILO Ou tput Le ak age
Current 1,2 ± 10 ± 10 ± 10 µA VCC = VCCMax
VCCQ = VCCQMax
VIN = VCCQ or GND
ICCS
VCC Standby Current
f or 0.1 3 and 0. 1 8
Micr on P roduct 1 7 15 20 50 150 250 µA VCC = VCCMax
CE# = RP# = VCCQ
or duri ng Prog ram/ E rase
Suspend
WP# = VCCQ or GND
VCC Standby Current
f or 0.25 Micron
Product 1 10 25 20 50 150 250 µA
ICCD
VCC Power-Down
Current for 0.13 and
0.18 Mic ron Product 1,2 7 15 7 20 7 20 µA VCC = VCCMax
VCCQ = VCCQMax
VIN = VCCQ or GND
RP# = GND ± 0.2 V
VCC Power-Down
Cu r rent for 0.25
Product 1,2 7 25 7 25 7 25 µA
ICCR
VCC Read Current for
0.13 and 0.18 M icron
Product 1,2,3 9 18 8 15 9 15 mA VCC = VCCMax
VCCQ = VCCQMax
OE# = VIH, CE# =VIL
f = 5 MHz, IOUT=0 mA
Inpu ts = V IL or VIH
VCC Read Current for
0.25 Mic ron Product 1,2,3 10 18 8 15 9 15 mA
IPPD VPP Deep Power-
Down Current 10.250.250.25µA
RP# = GND ± 0.2 V
VPP ≤ VCC
ICCW VCC Program Current 1,4 18 55 18 55 18 55 mA VPP =VPP1,
Program in Progress
82210301030mA
VPP = VPP2 (12v)
Program in Progress
ICCE VCC Erase Current 1,4 16 45 21 45 21 45 mA VPP = VPP1,
Erase in Progress
81516451645mA
VPP = VPP2 (12v) ,
Erase in Progress
Intel® Advanced+ Boot Bloc k Flash Memory (C3)
Datasheet I ntel® Advanced+ B oot Block Flash Mem ory (C3) M ay 2005
Order Number: 290645, Revisio n: 023 23
ICCES/
ICCWS
VCC Erase Suspend
Current for 0.13 and
0.18 Micron P roduct 1,4,5
7 15 50 200 50 200 µA CE# = VIH, E rase Suspend in
Progress
VCC Erase Suspend
Current for 0.25
M icr on Pr oduc t 10 25 50 200 50 200 µA
IPPR VPP Read Curre nt 1,4 2±15 2 ±15 2 ±15 µA VPP ≤ VCC
50 200 50 200 50 200 µA VPP > VCC
IPPW VPP Program Current 1,4 0.05 0.1 0.05 0.1 0.05 0.1 mA VPP =VPP1,
Program in Progress
8228 22 8 22mA
VPP = VPP2 (12v)
Program in Progress
IPPE VPP Erase Curre nt 1,4 0.05 0.1 0.05 0.1 0.05 0.1 mA VPP = VPP1,
E r as e in Progr e ss
82216451645mA
VPP = VPP2 (12v) ,
E r as e in Progr e ss
IPPES/
IPPWS VCC Erase Suspend
Current 1,4
0.2 5 0.2 5 0.2 5 µA VPP = VPP1,
Program or Erase Suspend in
Progress
50 200 50 200 50 200 µA VPP = VPP2 (12v) ,
Program or Erase Suspend in
Progress
Notes:
1.All currents are in RMS unless otherwise noted. Typical values at nominal VCC, TA= +25 °C.
2.The test conditi ons VCCMax, VCCQMax, VCCM in, an d VCCQMin refer to th e maximum or minimum VCC or VCCQ voltage l isted
at the top of each column. VCCMa x = 3.3 V f or 0.25µm 32-Mbit devic es.
3.A utoma ti c Powe r Saving s (APS) re duces ICCR to approximately standby levels in static operation (CMOS inputs).
4.Sampled, not 100% tested.
5.ICCES or ICCWS is specified with device de-selected. If device is read while in erase suspend, current draw is sum of ICCES and
ICCR. If the dev ice is re ad while in pr ogram susp end, curre nt draw is the sum of ICCWS and ICCR.
Table 6. DC Current Characteristics (Sheet 2 of 2)
Sym Parameter
VCC 2.7 V–3.6 V 2.7 V–2.85 V 2.7 V–3.3 V
Unit T est ConditionsVCCQ 2.7 V–3.6 V 1.65 V–2.5 V 1.8 V–2.5 V
Note Typ Max Typ Max Typ Max
Intel® Advanced + Boot Block Flash Memo ry (C3 )
May 2005 Intel® Advanced+ Bo ot Block Flash Memory (C3) Datasheet
24 Order Numbe r: 290645 , Revision: 023
6.2 DC Volt age Characteristics
Tab le 7. DC Voltage Characteristics
Sym Parameter
VCC 2.7 V–3.6 V 2.7 V–2.85 V 2.7 V–3.3 V
Unit Test ConditionsVCCQ 2.7 V–3.6 V 1.65 V–2.5 V 1.8 V–2.5 V
Note Min Max Min Max Min Max
VIL Input Low
Voltage –0.4 VCC *
0.22 V –0.4 0.4 –0.4 0.4 V
VIH Input High
Voltage 2.0 VCCQ
+0.3V VCCQ –
0.4V VCCQ
+0.3V VCCQ –
0.4V VCCQ
+0.3V V
VOL Output Low
Voltage –0.1 0.1 -0. 1 0.1 -0.1 0 .1 V VCC = VCCMin
VCCQ = VCCQMin
IOL = 100 µA
VOH Output High
Voltage VCCQ
–0.1V VCCQ –
0.1V VCCQ –
0.1V V
VCC = VCCMin
VCCQ = VCCQMin
IOH = –100 µA
VPPLK VPP Lock-
Out Voltage 1 1.0 1.0 1.0 V Comp le te Write
Protection
VPP1 VPP du ring
Program /
Erase
Operations
1 1.65 3.6 1.65 3.6 1.65 3.6 V
VPP2 1,2 11.4 12.6 11.4 12.6 11.4 12.6 V
VLKO
VCC Prog/
Erase
Lock
Voltage 1.5 1.5 1.5 V
VLKO2
VCCQ Prog/
Erase
Lock
Voltage 1.2 1.2 1.2 V
Notes:
1. Erase and Program are inhibited when VPP < VPPLK and not guar anteed o utside the valid VPP ranges of VPP1 and VPP2.
2.Applying VPP = 11.4 V–12 .6 V durin g program/ erase can on ly be done for a m axim um of 100 0 cyc les on the main bloc ks a nd
2500 cycles on the parameter blocks. VPP may be connected to 12 V for a total of 80 hours maximum.
Intel® Advanced+ Boot Bloc k Flash Memory (C3)
Datasheet I ntel® Advanced+ B oot Block Flash Mem ory (C3) M ay 2005
Order Number: 290645, Revisio n: 023 25
7.0 AC Characteristics
7.1 AC Read Characteristics
Table 8. Read Operations—8-Mbit Density
#SymParameter
Density 8 Mbit
Product 70 ns 9 0 ns 110 ns
VCC 2.7 V – 3.6 V 3.0 V – 3.6 V 2.7 V – 3.6 V 3.0 V – 3.6 V 2.7 V – 3.6 V
Note Min
(ns) Max
(ns) Min
(ns) Max
(ns) Min
(ns) Max
(ns) Min
(ns) Max
(ns) Min
(ns) Max
(ns)
R1 tAVAV Read Cycle Time 3,4 70 80 90 100 110
R2 tAVQV Address to
Output Delay 3,4 70 80 90 100 110
R3 tELQV CE# to Output
Delay 1,3,4 70 80 90 100 110
R4 tGLQV OE# to Output
Delay 1,3,4 20 30 30 30 30
R5 tPHQV RP# to Output
Delay 3,4 150 150 150 150 150
R6 tELQX CE# to Output in
Low Z 2,3,4 0 0 0 0 0
R7 tGLQX OE# to Outp ut in
Low Z 2,3,4 0 0 0 0 0
R8 tEHQZ CE# to Output in
High Z 2,3,4 20 20 20 20 20
R9 tGHQZ OE# to Output in
High Z 2,3,4 20 20 20 20 20
R10 tOH
Output Hold from
Ad dres s, CE #, or
OE# Change,
Whichever
Occurs First
2,3,4 0 0 0 0 0
Notes:
1.OE# may be delayed up to tELQV–tGLQV af ter th e falli ng ed ge of CE # wit hout impa ct on tELQV.
2. Sam pl ed , but not 100% te s t ed .
3.See Figure 9, “Read Operation Waveform” on page 28.
4.See Figure 11, “AC Input/Output Reference Waveform” on page 33 for timing measurements and maximum allowable input
slew rate.
Intel® Advanced + Boot Block Flash Memo ry (C3 )
May 2005 Intel® Advanced+ Bo ot Block Flash Memory (C3) Datasheet
26 Order Numbe r: 290645 , Revision: 023
Table 9. Read Operation s—16-Mb it Density
#SymParameter
Density 16 Mbit
Notes
Product 70 ns 80 ns 90 ns 110 ns
VCC 2.7 V–3.6 V 2.7 V–3.6 V 3.0 V–3.6 V 2.7 V–3.6 V 3.0 V–3.6V 2.7 V–3.6V
Min
(ns) Max
(ns) Min
(ns) Max
(ns) Min
(ns) Max
(ns) Min
(ns) Max
(ns) Min
(ns) Max
(ns) Min
(ns) Max
(ns)
R1 tAVAV Read Cycle Time 70 80 80 90 100 110 3,4
R2 tAVQV Address to Output
Delay 70 80 80 90 100 110 3,4
R3 tELQV CE# to Output Delay 70 80 80 90 100 110 1,3,4
R4 tGLQV OE# to Output Delay 20 20 30 30 30 30 1,3,4
R5 tPHQV RP# to Output Delay 150 150 150 150 150 150 3,4
R6 tELQX CE# to Output in Low Z 0000002,3,4
R7 tGLQX OE# to Output in Low Z 000000
2,3,4
R8 tEHQZ CE# to Output in High
Z20 20 20 20 20 20 2,3,4
R9 tGHQZ OE# to Output in High
Z20 20 20 20 20 20 2,3,4
R10 tOH
Output Hold from
Address, CE#, or OE#
Change, Whichever
Occurs First 000000
2,3,4
Notes:
1.OE# m ay be delayed up to tELQV–tGLQV after the falling edge of CE# without impact on tELQV.
2.Sampled, but not 100% tested.
3.See Figure 9, “Read Operation Waveform” on page 28.
4. See Figure 11, “AC Input/Output Reference Waveform” on page 33 for t im ing me asu r em ent s and ma x im um allow able
input slew rate .
Intel® Advanced+ Boot Bloc k Flash Memory (C3)
Datasheet I ntel® Advanced+ B oot Block Flash Mem ory (C3) M ay 2005
Order Number: 290645, Revisio n: 023 27
Table 10. Read Operations—32-Mbit Density
#SymParameter
Density 32 Mbit
Notes
Product 70 ns 90 ns 100 ns 110 ns
VCC 2.7 V–3.6 V 2.7 V–3.6 V 3.0 V–3.3 V 2.7 V–3.3 V 3 .0 V–3.3 V 2.7 V–3. 3 V
Min
(ns) Max
(ns) Min
(ns) Max
(ns) Min
(ns) Max
(ns) Min
(ns) Max
(ns) Min
(ns) Max
(ns) Min
(ns) Max
(ns)
R1 tAVAV Read Cycle Time 70 90 90 100 100 110 3,4
R2 tAVQV Address to Output
Delay 70 90 90 100 100 110 3,4
R3 tELQV CE# to Output Delay 70 90 90 100 100 110 1,3,4
R4 tGLQV OE# to Output Delay 20 20 30 30 30 30 1,3,4
R5 tPHQV RP # to Output Delay 150 150 150 150 150 150 3,4
R6 tELQX CE# to Output in Low Z 0000002,3,4
R7 tGLQX OE# to Output in Low Z 000000
2,3,4
R8 tEHQZ CE# to Output in High Z 20 20 20 20 20 20 2,3,4
R9 tGHQZ OE# to Output in High
Z20 20 20 20 20 20 2,3,4
R10 tOH
Output Hold from
Address, CE#, or OE#
Change, Whichever
Occu rs First 000000
2,3,4
Notes:
1.OE# may be delayed up to tELQV–tGLQV af ter th e falli ng ed ge of CE # wit hout impa ct on tELQV.
2. Sam pl ed , but not 100% te s t ed .
3.See Figure 9, “Read Operation Waveform” on page 28.
4. See Figure 11, “AC Input/Output Reference Wa veform” on page 33 for timin g measurements and maxi m um
allowa ble input slew rate.
Intel® Advanced + Boot Block Flash Memo ry (C3 )
May 2005 Intel® Advanced+ Bo ot Block Flash Memory (C3) Datasheet
28 Order Numbe r: 290645 , Revision: 023
Table 11. Read Operati ons — 64-M bit Density
#Sym Parameter
Density 6 4 Mbit
Unit
Product 70 ns 80 ns
VCC 2.7 V–3.6 V 2.7 V–3.6 V
Note Min Max Min Max
R1 tAVAV Read Cycle Time 3,4 70 80 ns
R2 tAVQV Addr ess to O utput Delay 3,4 70 80 ns
R3 tELQV CE# to Output Delay 1,3,4 70 80 ns
R4 tGLQV OE# to Output Delay 1,3,4 20 20 ns
R5 tPHQV RP# to Output Delay 3,4 150 150 ns
R6 tELQX CE# to Output in Low Z 2,3,4 0 0 ns
R7 tGLQX OE# to Output in Low Z 2,3,4 0 0 ns
R8 tEHQZ CE# to Output in High Z 2,3,4 20 20 ns
R9 tGHQZ OE# to Output in High Z 2,3,4 20 20 ns
R10 tOH Output H old from Address, CE #, or OE #
Change, Whichever Occurs First 2,3,4 0 0 ns
Notes:
1.O E# may be del ayed up to tELQV–tGLQV after the falling edge of CE# without impact on tELQV.
2.Sampled, but not 100% tested.
3.See F igure 9, “Read Ope ration Waveform” on page 28.
4.See Figure 11, “AC Input/Output Reference Wa veform” on pa ge 33 for timing measurements and maximu m
allowable input slew rate.
Figure 9. Read Operati on Wave form
R5
R10
R7
R6
R9R4
R8R3
R1
R2 R1
A
ddress [A]
CE# [E]
OE# [G]
WE# [W]
Data [D/Q]
RST # [P]
Intel® Advanced+ Boot Bloc k Flash Memory (C3)
Datasheet I ntel® Advanced+ B oot Block Flash Mem ory (C3) M ay 2005
Order Number: 290645, Revisio n: 023 29
7.2 AC Write Characteristics
Table 12. Write Operations—8-Mbit Density
#Sym Parameter
De ns ity 8 Mbit
Product 70ns 90 ns 1 1 0 ns
VCC
3.0 V – 3.6 V 80 100
2.7 V – 3.6 V 70 90 110
Note Min
(ns) Min
(ns) Min
(ns) Min
(ns) Min
(ns)
W1 tPHWL /
tPHEL R P# Hi gh Recovery to WE # (CE#) Going Low 4,5 150 150 150 150 150
W2 tELWL /
tWLEL CE# (WE#) Setup to WE# (CE#) Going Low4,50000 0
W3 tWLWH /
tELEH WE# (CE# ) Pulse Wid th 4,5 45 50 60 70 70
W4 tDVWH /
tDVEH D ata Setup to WE# (CE#) Going High 2,4,5 40 50 50 60 60
W5 tAVWH /
tAVEH Add r ess Setup to WE# (CE#) Going Hi gh 2,4,5 50 50 60 70 70
W6 tWHEH /
tEHWH CE# (WE#) Hold Time from WE# (CE#) High4,50000 0
W7 tWHDX /
tEHDX Data Hold Time from WE# (CE#) High 2,4,500000
W8 tWHAX /
tEHAX Address Hold Time from WE# (CE#) High2,4,500000
W9 tWHWL /
tEHEL WE# ( CE#) Pulse Width Hig h 2,4,5 25 30 30 30 30
W10 tVPWH /
tVPEH VPP Set up to WE# (C E#) Going High 3,4,5 200 200 200 200 2 00
W11 tQVVL VPP Hold from Valid SRD 3,400000
W12 tBHWH /
tBHEH WP# Setup to WE# (CE#) Going High 3,400000
W13 tQVBL WP# Hold from Valid SRD 3,400000
W14 tWHGL WE# High t o OE# Going Low 3,4 30 30 30 30 30
Notes:
1.Write pulse width (tWP) is defi ned fr om CE# or WE# goin g low (whichever goes low l ast) to C E# or WE# going high (w hich ever
goes hi gh fir st). Hence, tWP =t
WLWH =t
ELEH =t
WLEH =t
ELWH. Similarly, wr it e pulse wi dth high (tWPH) is def i ned f rom CE # or
WE# going high (w hichever goes high first) to CE # or WE # going low ( whichever goes low last) . Hen c e,
tWPH =t
WHWL =t
EHEL =t
WHEL =t
EHWL.
2.Refer to Table 22, “Command Bus Operations” on page 46 for valid AIN or DIN.
3. Sam pl ed , but not 100% te s t ed .
4.See Figure 11, “AC Input/Output Reference Waveform” on page 33 for timing measurements and maximum allowable input
slew rate.
5.See Figure 10, “Write Operations Waveform” on page 32.
Intel® Advanced + Boot Block Flash Memo ry (C3 )
May 2005 Intel® Advanced+ Bo ot Block Flash Memory (C3) Datasheet
30 Order Numbe r: 290645 , Revision: 023
Tab le 13. Write Operations— 16-M bit Density
#SymParameter
Density 16 Mbit
Unit
Product 70 ns 80 ns 90 ns 110 ns
VCC
3.0 V – 3.6 V 80 100
2.7 V – 3.6 V 70 80 90 110
Note Min Min Min Min Min Min
W1 tPHWL /
tPHEL RP# High Recovery to WE# (CE#) Going
Low 4,5 150 150 150 150 150 150 ns
W2 tELWL /
tWLEL CE# (WE#) Setup to WE# (CE#) Going Low 4,5 0 0 0 0 0 0 ns
W3 tWLWH /
tELEH WE# (CE#) Pulse Width 1,4,5 45 50 50 60 70 70 ns
W4 tDVWH /
tDVEH D ata Setup to WE# (CE#) Going Hi gh 2,4 ,5 40 40 50 50 60 60 ns
W5 tAVWH /
tAVEH Address Setup to WE# (CE#) Going High 2,4,5 50 50 50 60 70 70 ns
W6 tWHEH /
tEHWH CE# (WE#) Hold Time from WE# (CE#)
High 4,5 0 0 0 0 0 0 ns
W7 tWHDX /
tEHDX Data Hold Time from WE# (CE#) High 2,4,5 0 0 0 0 0 0 ns
W8 tWHAX /
tEHAX Add r es s Hol d Time f rom WE# (CE # ) Hi gh 2, 4, 5 0 0 0 0 0 0 ns
W9 tWHWL /
tEHEL WE# (CE#) Pulse Width High 1,4,5 25 30 30 30 30 30 ns
W10 tVPWH /
tVPEH VPP Setup to WE# (CE#) Going High 3,4,5 200 200 200 200 200 200 ns
W11 tQVVL VPP Ho ld fro m Val id SRD 3,4 0 0 0 0 0 0 ns
W12 tBHWH /
tBHEH WP# Set up to WE# (CE#) Goin g H igh 3,4 0 0 0 0 0 0 n s
W13 tQVBL WP# Ho ld from Valid SRD 3,4 0 0 0 0 0 0 ns
W14 tWHGL W E# Hig h to O E # G oin g Low 3, 4 30 30 3 0 30 3 0 30 ns
Notes:
1.Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to C E# o r WE # go ing h ig h (whi ch eve r
goes high first). Hence, tWP =t
WLWH =t
ELEH =t
WLEH =t
ELWH. Similarly, write pulse width high (tWPH) is d efined fr om CE# or
WE# going high ( whichever goes high first) to CE# or WE# going low (whichever goes low last). Hence,
tWPH =t
WHWL =t
EHEL =t
WHEL =t
EHWL.
2.Refer to Table 22, “Comm and Bus Ope rati ons” on page 46 for valid AIN or DIN.
3.Sampled, but not 100% tested.
4.See Figure 11, “AC Input/Output Reference Waveform” on page 33 for timing measur ements and maxi mum allowable input
slew rate.
5.See Figure 10, “Write Operations Waveform” on page 32.
Intel® Advanced+ Boot Bloc k Flash Memory (C3)
Datasheet I ntel® Advanced+ B oot Block Flash Mem ory (C3) M ay 2005
Order Number: 290645, Revisio n: 023 31
Tabl e 14. Write Operation s—32-Mb it Density
#Sym Parameter
Density 32 Mbit
Unit
Product 70 ns 90 ns 100 ns 1 10 ns
VCC
3.0 V – 3.6 V690 100
2.7 V – 3.6 V 70 90 100 110
Note Min Min Min Min Min Min
W1 tPHWL /
tPHEL RP# High Recovery to WE# (CE#)
Going Low 4,5 150 150 150 150 150 150 ns
W2 tELWL /
tWLEL CE# (WE#) Setup to WE# (CE#)
Going Low 4,5000000ns
W3 tWLWH
/
tELEH WE # (CE# ) Pulse Width 1,4,5 45 6 0 60 70 70 70 ns
W4 tDVWH /
tDVEH Data Setup to WE# (CE#) Going High 2,4,5 40 40 50 60 60 60 ns
W5 tAVWH /
tAVEH Ad dr ess Setup to WE# (CE#) Going
High 2,4,5506060707070ns
W6 tWHEH /
tEHWH CE# (WE#) Hold T ime from WE#
(CE#) High 4,5000000ns
W7 tWHDX /
tEHDX Data Hold Time from WE# (CE#)
High 2,4,5000000ns
W8 tWHAX /
tEHAX Addr ess Hold Time from WE# (CE #)
High 2,4,5000000ns
W9 tWHWL /
tEHEL WE# ( CE#) Pulse Width Hi gh 1,4,5 25 3 0 30 30 30 30 ns
W10 tVPWH /
tVPEH VPP Setup to WE# (CE#) Going High 3,4,5 200 200 200 200 200 200 ns
W11 tQVVL VPP Hold from Vali d SRD 3,4 0 0 0 0 0 0 ns
W12 tBHWH /
tBHEH WP# Setup to WE# (CE#) Going
High 3,4000000ns
W13 tQVBL WP# Hold from V a lid SRD 3,4 0 0 0 0 0 0 ns
W14 tWHGL WE # High t o OE# Going Low 3, 4 30 30 30 30 30 30 ns
Notes:
1.Write pulse width (tWP) is defi ned fr om CE# or WE# goin g low (whichever goes low l ast) to C E# or WE# going high (w hich ever
goes hi gh fir st). Hence, tWP =t
WLWH =t
ELEH =t
WLEH =t
ELWH. Similarly, wr it e pulse wi dth high (tWPH) is def i ned f rom CE # or
WE# going high (w hichever goes high first) to CE # or WE # going low ( whichever goes low last) . Hen c e,
tWPH =t
WHWL =t
EHEL =t
WHEL =t
EHWL.
2.Refer to Table 22, “Command Bus Operations” on page 46 for valid AIN or DIN.
3. Sam pl ed , but not 100% te s t ed .
4.See Figure 11, “AC Input/Output Reference Waveform” on page 33 for timing measurements and maximum allowable input
slew rate.
5.See Figure 10, “Write Operations Waveform” on page 32.
6.VCCMax = 3. 3 V f or 32 -M bit 0.25 Mic ron p r oduct .
Intel® Advanced + Boot Block Flash Memo ry (C3 )
May 2005 Intel® Advanced+ Bo ot Block Flash Memory (C3) Datasheet
32 Order Numbe r: 290645 , Revision: 023
Tab le 15. Write Operations— 64-M bit Density
# Symbol Parameter
Density 64 Mbit
UnitProduct 80 ns
VCC 2.7 V – 3.6 V Note Min
W1 tPHWL / tPHEL RP# High Recovery to WE# (CE#) Going Low 4,5 150 ns
W2 tELWL / tWLEL CE# (WE#) Setup to WE# (CE#) Going Low 4,5 0 ns
W3 tWLWH / tELEH WE# (CE#) Pulse Width 1,4,5 60 ns
W4 tDVWH / tDVEH Data Setup to WE# (CE #) Go ing High 2,4,5 40 ns
W5 tAVWH / tAVEH Address Setup to WE# (CE#) Going High 2,4,5 60 ns
W6 tWHEH / tEHWH CE# (WE#) Hold Time from WE# (CE#) High 4,5 0 ns
W7 tWHDX / tEHDX Data Hold Time from WE# (CE#) High 2,4,5 0 ns
W8 tWHAX / tEHAX A ddr es s Hol d Time f rom WE# (CE # ) Hi gh 2,4, 5 0 ns
W9 tWHWL / tEHEL WE# (CE#) Pulse Width High 1,4,5 30 ns
W10 tVPWH / tVPEH VPP Setup to WE# (CE#) Going High 3,4,5 200 ns
W11 tQVVL VPP Ho ld fro m Val id SRD 3 ,4 0 ns
W12 tBHWH / tBHEH WP# Setup to WE# (CE#) Going High 3,4 0 ns
W13 tQVBL WP# Ho ld from Va li d SRD 3, 4 0 ns
W14 tWHGL W E # Hig h to O E # Goi n g Low 3, 4 30 ns
Notes:
1. W rite pul se wid th (t WP) is de fine d fr om CE# or WE# go in g low (whi ch ever go es low las t) to CE# or W E# go ing h ig h (w hich ev er
goes high fir s t). Hence, tWP =t
WLWH =t
ELEH =t
WLEH =t
ELWH. Similarly, write pulse widt h hi gh (tWPH) is defined from CE# or
WE# going high ( whichever goes high first) to CE# or WE# going low (whichever goes low last). Hence,
tWPH =t
WHWL =t
EHEL =t
WHEL =t
EHWL.
2.Refer to Table 22, “Comm and Bus Ope rati ons” on page 46 for valid AIN or DIN.
3.Sampled, but not 100% tested.
4.See Figure 11, “AC Input/Output Reference Waveform” on page 33 for timing measur ements and maxi mum allowable input
slew rate.
5.See Figure 10, “Write Operations Waveform” on page 32.
Figure 10. Writ e Ope rations Waveform
W10
W1
W7W4
W9W9
W3W3
W2
W6
W8W5
A
ddress [A]
CE # [E ]
WE# [W]
OE# [G]
D a ta [D /Q]
RP # [P ]
Vpp [V]
Intel® Advanced+ Boot Bloc k Flash Memory (C3)
Datasheet I ntel® Advanced+ B oot Block Flash Mem ory (C3) M ay 2005
Order Number: 290645, Revisio n: 023 33
7.3 Erase and Program Timings
Tabl e 16. Erase and Progr am Timings
7.4 AC I/O Test Conditions
Note: Input timing begins, and output timing ends, at VCCQ/2. Input rise and fall times (10% to 90%) < 5 ns.
Worst-cas e spee d conditions are when VCC = VCCMin.
Symbol Parameter VPP 1.65 V–3.6 V 11.4 V–12.6 V Unit
Note Typ Max Typ Max
tBWPB 4-KW Param et er Block
Word Program Time 1, 2, 3 0.10 0.30 0.03 0.12 s
tBWMB 32-KW Main Block
Word Program Time 1, 2, 3 0.8 2.4 0.24 1 s
tWHQV1 / tEHQV1
Wo rd Pr ogram T ime fo r 0.13
and 0.18 Micron Product 1, 2, 3 12 200 8 185 µs
Wo rd Pr ogram T ime fo r 0.25
Micron Product 1, 2, 3 22 200 8 185 µs
tWHQV2 / tEHQV2 4 -KW Par am et er Block
Erase Time 1, 2, 3 0.5 4 0.4 4 s
tWHQV3 / tEHQV3 32-KW Main Block
Erase Time 1, 2, 3 1 5 0.6 5 s
tWHRH1 / tEHRH1 Program S uspen d Latency 1,3 5 10 5 10 µs
tWHRH2 / tEHRH2 Erase Suspend Latency 1,3 5 20 5 20 µs
Notes:
1.Typi cal values me asured at TA= +25 °C and nominal voltages.
2.Excludes external system-level overhead.
3.Sampled, but not 100% tested.
Figure 11. AC In put/Ou tput Reference Waveform
V
CCQ
0V
V
CCQ
/2 V
CCQ
/2
Test Points
Input Outpu
t
Intel® Advanced + Boot Block Flash Memo ry (C3 )
May 2005 Intel® Advanced+ Bo ot Block Flash Memory (C3) Datasheet
34 Order Numbe r: 290645 , Revision: 023
Note: See Tabl e 17 for componen t values .
7.5 Device Capacitance
TA = 25 °C , f = 1 MHz
Figure 12. Transient Equivalent Testing Load Circuit
Device
Under Test
V
CCQ
C
L
R
2
R
1
Out
Tab le 17. Test Configuration Componen t Values for Worst-Case Speed Con ditions
Test Configuration CL (pF) R1 (kΩ)R
2 (kΩ)
VCCQMi n Stand ar d Test 50 25 25
Note: CL in cludes jig capacitan ce.
Table 18. Device Capacitance
Symbol Parameter§Typ Max Unit Condition
CIN Input Capacitance 6 8 pF VIN = 0.0 V
COUT Output Cap acitance 8 1 2 pF VOUT = 0.0 V
§Sampled, not 100% tested.
Intel® Advanced+ Boot Bloc k Flash Memory (C3)
Datasheet I ntel® Advanced+ B oot Block Flash Mem ory (C3) M ay 2005
Order Number: 290645, Revisio n: 023 35
8.0 Power and Reset Specifications
Intel® flash devi ce s have a ti ere d approach to powe r savings that can significan tly reduc e ove rall
system power consumption. The Automatic Power Savings (APS) feature reduces power
cons ump tion when the device is se lec te d but idle. If CE# is deas s ert ed, the flash e nters its standb y
mode , where curre nt cons um ption is even lower. If RP# is deas serted, the flash enter deep power-
down mode for ultra-low curre nt consumption. The combin at ion of these featu res ca n min im iz e
memory powe r consum ption, and therefore, overall syst em power c ons umption.
8.1 Active Power (Program/Erase/Read)
With CE# a t a logic-low leve l and RP # at a logic-h igh level , the device is in the acti ve mode. Refer
to th e D C Charac teris tic tables fo r ICC curr en t values. Ac tive power is the largest c o ntr ibutor to
overa ll system power c ons um ption. Minimizing the ac tive curre nt could have a profound effect on
syste m power consum ption, especially for batte ry-operated devices.
8.2 Automatic Power Savings (APS)
Automati c Power Saving s provide s low-powe r operat ion during read mode. After da ta is re ad fr om
the memory array and the address lines are idle, APS circuit ry places the dev ice in a mode where
ty pical cur r ent is com p arable to ICCS. The flash stays in this static state with outputs valid until a
new location is read.
8.3 Standby Power
When CE# is at a logic-high level (VIH), the flash memory is in standby mode, which disables
much of the device’s circu itry and s ubstanti al ly reduces power cons um ption. Outputs are placed in
a high-impedance stat e inde pendent of the st atu s of th e OE# signa l. If CE# transitions to a logic-
high level during Er ase or Progr am opera tions, the devi ce will continue to perform the operation
and consum e c orrespondin g act ive power until the operat ion is completed.
Syste m e ngineers shoul d ana lyze the breakdown of standby time versus active time and qua ntify
the respective power consumption in each mode for their specif ic appl ication. This approach will
provide a more accurate measure of application-specific power and energy requirements.
8.4 Deep Pow er-Do wn Mode
The deep powe r-down mode is activated when RP# = VIL. During rea d modes , RP# going low de-
selec ts the memory and pla ce s th e outputs in a high-impedance state. Recovery from deep power-
down requir es a min im um time of tPHQV for r ead o perations, an d tPHWL/tPHEL for write operations.
During program or erase modes, RP# trans itioning low aborts the in-progress operation. The
memory co ntents of the addr ess bein g progra mmed or the bl ock bein g era sed are no longe r valid as
the data integrity ha s been compromised by the ab ort. During deep power-down, all internal
circ uits are switc he d to a low-power savings mode (RP # tra nsi tioning to VIL or turning off power
to t he d evice clears t he Statu s R eg ister) .
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8.5 Power and Reset Considerations
8.5.1 Power-Up/Down Characteristics
To prevent any con d ition that may resu lt in a spurious write or erase ope rat ion, Intel re com me nds
to power-up VCC and VCCQ tog ether. Conversely, VCC and VCCQ must powe r-down tog ether.
I nte l also recommend s th at you power-up VPP with or aft er VCC ha s reac hed VCCmin.
Conversely, VPP must powerdo wn with or slightl y befor e VCC.
If VCCQ and/or VPP are not connected to the VCC supply, then VCC must attain VCCmin before
applying VCCQ and VPP. Device inpu ts must not be driven before supply voltage reache s
VCCmin.
Power supply transitions must only occur when RP# is low.
8.5.2 RP# Connected to System Reset
The use of RP# during syste m rese t is important with aut o m ated program/erase devic es since the
system reads from the flash m emory when it comes out of reset. If a CPU reset oc curs without a
f lash m emory res et, prope r CPU initializat ion will not occur becaus e the flash memory may be
pr oviding sta tus info rmation ins tea d of array data. Intel recommend s connect ing RP# to th e system
CPU RES ET # signal to allow prope r CP U/flash initi alization following syst em reset .
Syst em desi gners mus t guard agai nst spuri ous writ es when VCC vol tages ar e above VLKO. Because
both W E# an d CE# mus t be low for a comman d write , dri ving either sign al to VIH will inhibit
writes to the device. The CUI architecture provides additional protection since alteration of
memory contents can only occur after successful completion of the two-step command sequences.
The device is also di sabled until RP# is brought to VIH, regardless of the state of its control inputs.
By holding the devi ce in reset during power-up/down, inval id bus conditions during power-up can
be masked, providing yet anothe r level of memory prot ec tion.
8.5.3 VCC, VPP and RP# Transitions
The C U I la t ch es command s as issu ed by system software and is not altered by VPP or CE#
transitions or WSM actions. Its defaul t state upon power -up, aft er exit from reset mode or after
VCC trans itions abov e VLKO (Lockout voltage), is read- array mode.
After any progra m or Bl ock-Erase operat ion is complete (even after VPP transitions down to
VPPLK), the CUI must be reset to read-a rray mode by the Read Arra y command if acce s s to the
fla sh-memory array is desired.
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8.5.4 Reset Specifications
8.6 Power Supply Decoupling
Flas h me mory power-switching char acterist ics require careful devic e decoupling . Sys tem
des igne rs sho uld consider the fol lowi ng three supply current issues:
•S tandby curren t lev el s (ICCS)
•Read current levels (ICCR)
•Trans ie nt pea ks produced by fall ing and rising edge s of CE#.
Table 19. Reset Specifications
Symbol Parameter VCC 2.7 V – 3. 6 V Unit Notes
Min Max
tPLPH RP# Low to Reset during Read
(If RP# is tied to VCC, this specification is not
applicable) 100 ns 1, 2
tPLRH1 RP# Low to R eset dur ing Block Erase 22 µs 3
tPLRH2 RP# Low to Reset during Program 12 µs 3
Notes:
1 .If t PLPH is < 100 ns the device m ay still reset but thi s is not guara nteed.
2.If RP# is asserted while a Block Erase or Word Program operation is not executing, the reset
will complete within 100 ns.
3.Sampled, but not 100% tested.
Figure 13. Reset Op erati on s Wave form s
IH
V
IL
V
RP # (P )
PLPH
t
IH
V
IL
V
RP # (P )
PLPH
t
(A) Reset during Read Mode
Abort
Complete PHQV
tPHWL
tPHEL
t
PHQV
tPHWL
tPHEL
t
(B) Reset du ring Progr am or Blo ck E r ase, <
PLPH
tPLR
H
t
PLRH
t
IH
V
IL
V
RP# (P)
PLPH
t
Abort
Complete PHQV
tPHWL
tPHEL
t
PLRH
t
Deep
Power-
Down
(C) Reset P r ogr am or Bloc k Erase, >
PLPH
tPLRH
t
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T r ansient curren t magnit udes depend on the device outputs ’ capacit ive and induc tive loadin g. Two-
line control and proper decoupling capacitor selection will suppress these transient voltage peaks.
Each flash device should ha ve a 0.1 µF cera mi c capa citor conne ct ed betwee n ea ch VCC and GND,
and between its VPP and VSS. These high-fre quency, inherently lo w- inductance capa citors sh ould
be pl aced as cl ose as po ssible to th e pa ck ag e leads.
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9.0 Device Operations
The Intel® Advanced+ Boot Block Flash Memory (C3) device use s a CUI and automa te d
algori thm s to simp lify Pro gram and Erase operatio ns . Th e CUI allows for 100% CMOS -level
control inputs and fixed power supplies during erasure and programming.
The internal WSM completely automates Program and Erase operations while the CUI signals the
star t of an opera tion and the Stat us Re gis ter reports dev ic e status. T he CUI han dles the WE#
interface to the da ta a nd address latche s as well as system status r eque s ts during WSM operati on.
9.1 Bus Operations
The Intel® Advanced+ Boot Block Flash Memory (C3) device performs read, program, and eras e
operations in-sys te m through the loc al CPU or microc ontroller. Four contro l pins (CE #, OE# ,
WE#, and RP#) mana ge the da ta fl ow in and out of the flas h device. Table 20 on page 39
summar izes th ese bu s o per ations.
9.1.1 Read
When performing a read cyc le , CE# and OE# must be ass ert ed; WE# and RP# must be deass erted.
CE# is the devic e selection cont rol; when active low, it enables the flash m emory device. OE# is
the dat a out put control; when low, data is output on DQ[15:0]. See F igure 9, “Read Opera ti on
Waveform” on page 28.
9.1.2 Write
A write cycle occu rs when both CE# and WE# are low; RP# and OE# are high. Commands are
issued to the Command User Interface (CUI). The CUI does not occupy an addressable memory
lo ca tion. Address and dat a are latched on the ris ing edge of the WE# or CE# pu ls e, wh ichever
occur s first. See Figure 10, “Write Operations Waveform” on pa ge 32.
9.1.3 Output Disable
With O E# at a logic-high level (VIH), the device outputs are dis abl ed. DQ[15:0] are placed i n a
high-impedance state.
Tab l e 20 . B us Op er ations
Mode RP# CE# OE# WE# DQ[15:0]
Read VIH VIL VIL VIH DOUT
Write VIH VIL VIH VIL DIN
Output Disable VIH VIL VIH VIH High-Z
Standby VIH VIH XXHigh-Z
Reset VIL XXXHigh-Z
Note: X = Don’t Care (VIL or VIH)
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9.1.4 Standby
Des el ecting the de vice by bringin g CE# to a logic -high level (VIH) places the de vice in standby
mode, which substantially reduces device pow er consumption without any latency for subsequent
r ea d acces s es. In standby, outputs are plac ed in a high-impedance state independent of OE# . If
des el ec ted during a Pro gram or Era s e oper ation, the device continues to consum e active power
until the Program or Erase operation is complete.
9.1.5 Reset
From read mode, RP# at VIL for time tPLPH desele cts the memory, places o utput drivers in a high-
imp eda nce s ta te , and turn s off all inte rnal circuits. After ret urn from rese t, a time tPHQV is required
u ntil the ini tial read -acce ss ou tputs are val id. A del ay (tPHWL or tPHEL) is require d after return from
reset before a write cycle can be initiated. After this wake-up inte rval, no rmal operat ion is restore d.
The CUI resets to read-array mode, the S tatus Register is set to 0x80, a nd all blocks are locked. S ee
Figure 13, “Reset Operations Waveforms” on page 37.
If RP# is taken low for time tPLPH during a Pro gram or Era s e operation, the operation will be
aborted; the me mory contents at the abort ed locatio n (for a program) or block (for an erase) are no
longer valid, since the data may be partially erased or written. The abort process goes through the
f ollowing seq uenc e:
1. Whe n RP # goes low, the device shuts down the opera ti on in progress, a process which tak es
time tPLRH to complete.
2. After time tPLRH, t he part will either re s et to rea d-array mode (if R P # is asse rte d during tPLRH)
or enter reset mode (if RP# is deasserted aft er tPLRH). See Figure 13, “Reset Operations
Waveforms” on page 37.
I n both ca s es , after returnin g from an abort ed ope ration, the rel eva nt time tPHQV or tPHWL/tPHEL
mus t be obse rve d before a Read or W rite opera tion is initiated, as discus s ed in the previous
paragraph. However, in this case, these delays are referenced to the end of tPLRH rather than when
RP# goes high.
As wit h any aut omat ed devi ce, it is impor tant to assert RP# duri ng a system rese t. Wh en the sys tem
com es out of reset, the processor rea ds from the flash memory. Automated flash memories provide
status information when read during Program or Block-Erase operations. If a CPU reset occurs
with no flash memor y reset, proper CPU init ializa tion may not occur bec ause the flash mem o ry
ma y be provid ing sta tus inform ation inste ad of arr ay data . Inte l® flash memori es allow pr oper CP U
initialization f ollowing a syste m re se t through th e use of the RP# input. In this applicati on, RP# is
controlled by the same RESET# signal that resets the system CPU.
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10.0 Modes of Operation
10.1 Read Mode
The flash m em ory ha s fo ur rea d mo des (re ad a rray, read identifier, read statu s, and CFI query ) and
two write modes (program and erase). Three additional modes (erase suspend to program, erase
suspend to read, and program suspend to read) are available only during suspended operations.
Table 22, “Comma nd Bus Opera ti ons ” on pa ge 46 an d Table 23, “Comm and Codes and
Descriptio ns” on page 47 summa r iz e th e command s u s ed for th ese mo des.
Appendix A, “Write St ate Machine St ates” on page 54 is a comprehensive chart showing the state
transitions.
10.1.1 Read Array
Wh en RP# transi tions from VIL (reset) to VIH, the device defaults to read-array mode and will
res pond to the read-control inputs (CE# , add res s inputs, and OE#) with out any additional CUI
commands.
When the de vice is in read array mo de, four control signals control data output.
•WE# mus t be lo gic high (VIH)
•CE# must be logi c low (VIL)
•OE# must be logic low (VIL)
•RP# must be logic high (VIH)
In addition, the addre s s of th e desired loca tion must be appli ed to the a ddress pins. If the de vice is
not in read-array mode, as would be the case after a Program or Erase operation, the Read Array
command (0xFF) must be issued to the CUI before array reads can occur.
10.1.2 Read Identifier
The re ad-ide ntifie r mode outpu ts thr ee type s of in formation: the manufacturer/device identifier, the
block locking status , and t h e protection regist er. The devic e is switched to this mode by issuing the
Re ad I dent ifi er com ma nd (0 x 90). On ce in th is mo de, rea d c ycl es f rom ad dres ses sho wn i n Table 21
retrieve the specified information. To return to read-array mode, issue the Read Array com mand
(0xFF).
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10.1.3 CFI Query
The CFI query mode outputs Com mon Flas h Interface (CFI ) data after issuin g the Read Query
Command (0x98). T he CF I data structure contains information such as block size, density,
com mand se t, an d electri cal specific atio ns. Once in this mode , read c ycles fr om address es shown in
Appendix C, “Commo n F lash Interface,” retrie ve the specif ied informa tion. T o return to re ad-array
mode , iss ue the Read Arra y com mand (0xF F ).
10.1.4 Read Status Register
The S ta tus Register indicate s th e s tat us of devi ce op era tions and the success/fa ilure of that
op era tion. The Rea d Status Register (0x70) command c auses subsequent reads to output data from
the S ta tus Reg is te r unti l anot her comma nd is issu ed. To return to readi ng from the array, issu e a
Rea d Array (0xFF) com m and.
The S ta tus Register bit s ar e output on DQ[7:0]. Th e uppe r byte, DQ[15:8], output s 0x00 when a
Read Status Register command is issued.
Table 21. Device Identification Codes
Item Address1
Data Description
Base Offset
Man ufacturer ID Block 0x00 0x0089
Device ID Block 0x01
0x88C0 8-Mbit Top Boot Device
0x88C1 8-Mbit Bottom Boot Device
0x88C2 1 6- M bit Top Boot D evic e
0x88C3 16-Mbit Bottom Boot Device
0x88C4 3 2- M bit Top Boot D evic e
0x88C5 32-Mbit Bottom Boot Device
0x88CC 64-Mbit Top Boot Device
0x88CD 64-Mbit Bottom Boot Device
Block Lock Status2Block 0x02 DQ0 = 0b0 Blo ck is unlocked
DQ0 = 0b1 Block is locked
Block Lock- D own Status2Block 0x02 D Q 1 = 0b0 Blo ck is not locked- down
DQ1 = 0b1 Block is locked down
Protection Register Lock Status Block 0x80 Lock Data
Pro tecti on Regi ster Block 0x8 1 - 0x88 Regis ter Data Multiple reads required to read the
ent ir e 128- b i t P rotec tion Reg ist e r.
Notes:
1.The add r ess is c onstr ucted f rom a bas e add r ess plus a n offset. For exam ple, t o read the Block Lo ck Status for block numb er
38 in a bo tto m bo ot de vice , s et the a dd res s to 0x 0F 8000 pl us th e offset (0x02), i.e. 0x0F8002. Then examine DQ0 of the data
to determine if the block is locked.
2.See Se ction 11.2, “Reading Bl ock-Lock Status” on page 5 0 for valid lock status.
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The co ntents of the S ta tus Register are lat che d on the fall ing edge of OE# or CE# (whichever
occurs last) which prevents possible bus errors tha t might occur if S ta tus Register cont ent s chan ge
while being read. CE# or OE# must be toggled with each subsequent status read, or the Status
Regis ter will not indicate com pletion of a Progra m or Er ase ope ration.
When the WSM is active, SR [ 7] w ill indi cate the status of the WSM; the r emaining bits in the
S ta tus Regi s ter indi ca te whether the WSM was successful in perform ing the preferred ope ration
See Table 24, “ Status Regis te r Bit Definition” on page 48.
10. 1. 4.1 Cl ear Status Reg i ster
The WSM can set S ta tus Register bits 1 through 7 and can clear bits 2, 6, and 7, but the WSM
cannot clear S ta tus Register bits 1 , 3, 4 or 5. Because bits 1, 3, 4, and 5 indicate various error
conditions , the s e bits can be cleared only through the Cle ar S ta tus Register (0x50) command. By
allowing the system software to control the resetting of these bits, several operations may be
performed (such as cumulatively programming several addresses or erasing multiple blocks in
sequence) before reading the Status Register to determine if an error occurred during that series.
Clea r the S ta tus Register befor e beg inning another comma nd or sequence. The Read Array
co mman d must be i ssued before data can be read f r o m th e memo r y array. Resetting the dev ice also
clears the Status Register .
10.2 Program Mode
Programming is executed using a two-write cycle sequence. The Program Setup command (0x40)
is issued to the CUI, followed by a second write that specifies the address and data to be
programmed. The WSM will execute a sequence of internally timed events to program preferred
bits of the addressed location, then verify the bits are sufficiently programm ed. Programming the
memory results in spec ific bits within an address loc ation being ch ange d to a “ 0.” If users att em pt
to pr ogram “1”s, the memory cel l co ntents do not ch ange and no error occurs.
The St atus Register indicat es program ming stat us. Whil e the program seq uence e xecutes , status bit
7 is “0. ” The S tatus Re gi ster can be polle d by toggl ing either CE# or OE#. W hile pr ogramming , the
only val id co mm and s a re Re ad Status Regi ster, Program Su spend, and Program Resume .
When programming is compl et e, the pro gram -s tatus bits must be checked. If the programm ing
opera tion was unsuccess ful, SR[4] is set to indicat e a program failure. If SR[3] i s set, then VPP was
not with in a cceptabl e limit s, and the WSM did not e xecut e the prog ram comm and. If SR[1] is set, a
program operation was attempted on a locke d block and the operat ion was aborted.
The Status Regis ter should be cl ea red before attem pting the nex t oper ation. Any CUI instruc tion
can follow aft er programming is complete d; however, to prevent inadvertent S ta tus Regist er re ads,
be sure to reset the CUI to read-array mode.
10.2.1 12-Volt Production Programming
Whe n VPP is betw ee n 1.65 V and 3.6 V, all program and er ase current is drawn through th e VCC
pin.
Note: If VPP is driven by a logic signal, VIH min = 1.65 V. That is, VPP must remain above 1.65 V to
perform in-sys te m flash mo difi ca tions.
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When VPP is connecte d to a 12 V power supply, the devi ce draws program and erase current
directly from the VPP pin. This eliminates the need for an external switching transi st or to c ontrol
VPP. F igure 16 on page 53 shows examples of how the flash power supplies can be configured for
various usage models.
The 1 2 V V PP mode enhances programming performance during the short period of time typically
f ound in m anufacturi ng processes; however, it is not intended for ext ende d use. You cna apply
12 V to VPP during Program and Eras e operations for a maximum of 1000 cy cl es on the mai n
blocks and 2500 cycles on the parameter blocks . VPP ma y be c onne cted to 12 V for a total of 80
hours ma xim um. Stress ing the devic e be yond these limi ts ma y cau se perm anent damage .
10.2.2 Suspending and Resuming Program
The Program Suspend command halts an in-progress program opera tion so that data can be read
f rom ot her locatio ns of memory. Once the progra m mi ng process starts , is su ing the Progra m
Suspe n d command to t h e CUI reques ts th at the WSM suspend the pr ogram seque n ce at
pr edeterm ined poi nts i n the prog ram algori thm. The devic e conti nues to out put S tatus R egiste r data
after the Program Su sp end c omm an d is issue d. Polling SR [7] and SR[2] will determi ne whe n the
pr ogra m ope rat ion has been suspended (both will be set to “1”). The program-suspend lat enc y is
specified with tWHRH1/tEHRH1.
A Read-Ar ray co mmand can now be issued to the CUI to read dat a from bloc ks othe r than that
which is suspended. The only other va lid commands wh ile program is s us pended are Read Status
Register, Read Identifier, CFI Query, and Program Resume.
After the Program Resume com ma nd is is s ued to the fla s h me mory, the WSM will conti nue with
the programming process and SR[2] and SR[7] will automati ca lly be clea red. The devi ce
automatically outputs Sta tus Register dat a when read (see Figure 18, “ P rogram Susp end / Re s ume
Fl owcha rt” on page 57) after the Program Resume command is issued. VPP mus t remain at th e
same VPP level used for program while in program-suspend mode. RP# must a ls o remain at VIH.
10.3 Er a se Mo de
To era se a block, issue th e Era se Set-up and Erase Conf irm com mands to the CUI, al ong with an
address ident ifying the block to be erase d . Th is addre s s is latched inte rnally when the Erase
Confi rm comma nd is is sued. Block er asure results in a ll bit s withi n th e block bei ng set to “ 1.” Only
o n e b lock can b e erased at a time . The WSM w ill execute a sequence of inte r n ally timed ev ents to
p rogram all bits within the block to “0, ” era s e al l bits within the bl ock to “1,” then v eri fy that all
bits within the block are sufficiently erased. While the erase executes, status bit 7 is a “0.”
When the Status Register indic ates that er asure is complete, chec k the eras e-st atus b it to verify tha t
the Erase operation was successful. If the Erase operation was unsuccessful, SR[5] of the Status
Register will be se t to a “1 ,” indic ating an erase failure. If VPP is no t wi thin ac ceptab le limits after
t he Eras e Conf ir m com mand was iss u ed, the WSM will not exec u te the erase sequ en ce; in stead ,
SR[ 5] of th e S tat us Reg iste r is set t o ind ica te an e rase erro r , and SR [3] is set to a “ 1” to ide nt ify t hat
VPP supply voltage is not within acceptable limits.
After an Erase operation, cle ar the Status Regi st er (0x50) before atte mpt ing the ne xt operation.
Any CU I ins truction c an follow after erasure is com pleted; howe ver, to preve nt inadvertent stat us -
r egi st er re ads, Intel recomme nds tha t you place the flash in re ad-a rray mode after the erase is
complete.
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10.3.1 Suspending and Resuming Erase
Since an Erase operation requires on the order of seconds to complete, an Erase Suspend command
is provide d to allow erase-sequence interruption to read data from—or program data to— another
bl o ck in mem o r y. Once th e er ase sequ en ce is start ed, issuing the Erase Susp end comman d to the
CUI suspends the erase sequence at a predetermined point in the erase algorithm. The Status
Regis ter indicates if/when the Era se operation has been suspended. Eras e-s uspend la tency is
specified by tWHRH2/tEHRH2.
A Read Array or Program comma nd can now be issued to the CUI to read/progra m data from/ to
blocks other than tha t which is suspended. This nested Program comman d can subse quently be
suspended to read yet another location. The only valid commands while Erase is suspended are
Read Status Register, Rea d Identif ier, CFI Query, Progr am Setup, Program Resum e, Erase
Res ume, L ock Bl ock, Unlock Blo ck, and Lo ck-Do wn Bloc k. During erase-sus pend mode, the
devic e can be placed in a ps eudo-sta ndby mode by tak ing CE# t o VIH, which redu ces activ e current
consumption.
Era s e R esu me con ti n ue s the er as e seq u enc e w h en CE # = VIL. Simil ar to the end of a standard
Erase opera tion, the St atus Register m us t be re ad and cleared before the next ins truction is issued.
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Bus operations are defined in Table 20, “Bus Operations” on page 39.
Tab le 22. Comm an d Bus Operati ons
Command Notes First Bus Cycle Second Bus Cycle
Oper Addr Data Oper Addr Data
Read Array 1,3 Write X 0xFF
Read Identifier 1,3 Write X 0x90 Read IA ID
CFI Query 1,3 Write X 0x98 Read QA QD
Read Sta tus Re gister 1,3 Writ e X 0x7 0 Read X SR D
Cle ar Sta tus Re gister 1,3 Write X 0x5 0
Program 2,3 Write X 0x40/
0x10 Write PA PD
Block Erase/Confirm 1,3 Write X 0x20 Write BA D0H
Progr am /E rase S us pen d 1, 3 Write X 0x B0
Progr am /E rase R es um e 1, 3 Writ e X 0xD0
Lock Block 1,3 Wr ite X 0x60 Write B A 0x01
Unlock Block 1,3 Write X 0x60 Write BA 0xD0
Lock-Do wn Blo ck 1,3 Wr it e X 0x6 0 Write B A 0x2F
Prot e ct ion Pr ogr am 1,3 Wr it e X 0xC 0 Writ e PA PD
X = "Don’t Care" PA = Prog Addr BA = Block Addr IA =Identifier Addr. QA = Query Addr.
SRD = Status Reg.
Data PD = Pr o g D ata I D = Ide ntifier D ata Q D = Que r y Dat a
Notes:
1.Follo wing the Read Identi fier or CFI Q uery com m and s, read operatio ns ou tp ut devic e identi ficat ion data or
CFI query information, respectively. See Section 10.1.2 and Section 10.1.3.
2.E it her 0x40 or 0x10 command is valid, but th e Intel standard i s 0x40.
3.When writi ng c om mands, t he u pper d ata bus [DQ8-DQ1 5] shou ld be eith er VIL or VIH, to minimize current
draw.
Intel® Advanced+ Boot Bloc k Flash Memory (C3)
Datasheet I ntel® Advanced+ B oot Block Flash Mem ory (C3) M ay 2005
Order Number: 290645, Revisio n: 023 47
Table 23. Co mmand Codes and Descriptions
Code
(HEX) Device Mode Command Description
FF Rea d Array This command places the device i n read- array m ode , whic h outputs array data on the data pins.
40 Program Set-Up
Thi s is a two-cycle command . The firs t cycle pr epa r es the CUI for a program opera ti on. The
sec ond cycle lat ches ad dr esse s and d at a informat ion and initiates th e WSM to exec ute the
Pro gr am al gorithm. The fl ash outputs Statu s Register data w hen CE# or OE # is toggled. A Read
Array command is required after programming to read array data. See Section 10.2, “Program
Mod e” on page43.
20 E rase Set-U p T hi s is a two-cycl e command. It pr epa r es the C UI for t he Era se Conf ir m comman d. If the next
command is not an Erase Confirm command, then the CUI will (a) set both SR.4 and SR.5 to “1,”
(b) place the device into the read-S tatus Register mode, and (c) wait for another command. See
Section 10.3, “Erase Mode” on page 44.
D0
Eras e C onfi r m
Program/Erase
Resume
Unlock Block
If the previous command w as an Erase Set-Up command, then the C UI wil l close the address and
dat a lat ch es and b eg in er as ing t he blo ck ind ic ated on the ad dres s pins . Du ring pro gram /e ras e, th e
device wi ll re spon d only to th e Read Status Regist er, Progr am Su spend and Er ase Suspend
commands, and will output Status Register data when CE# or OE# is toggled.
If a Pr ogram or Erase op er ation was p reviously suspended, this command wil l re sume t hat
operation.
If the previous command was Block Unlock Set-Up, the CUI will latch the address and unlock the
block indicated on the address pins. If the block had been previously set to Lock-Down, this
operati on wi ll have no eff ect. (See Section 11.1)
B0 Program Suspend
Eras e S us pend
Issui n g this com m and w ill be gin to susp end the cu rre ntl y execu t ing Pro gra m/ Eras e ope rat ion. The
S ta tu s Re gist er wi ll i ndic ate w hen th e ope rat ion ha s been su ccess fu lly s uspen de d by set tin g eit her
the program-suspend SR[2] or erase-suspend SR[6] and the WSM status bit SR[7] to a “1”
(ready). The WSM will continue to idle in the SUSPEND state, regardless of the state of all input-
cont rol pins ex ce pt RP #, wh ich will i mme diat ely sh ut dow n the WSM and t he re mai nder of t he chi p
if RP# is dr iven to VIL. See Sect ions 3.2.5 .1 and 3.2.6 .1.
70 Read Status
Register
This comman d places the device into read -Stat us Registe r m ode. R eading the device w ill ou tput
the content s of th e Status Regist er, regar dless of t he ad dr ess p r esen ted to the device. The device
automaticall y en te r s t his mode aft er a P rogr am or E r ase o perat ion has been initiated. See Section
10.1. 4, “Read Stat us Re gister” on page 42 .
50 Clear Status
Register The WSM c an se t the bloc k- lock status SR[1], V PP Status SR [3 ], program status SR[4], and erase-
sta tus SR [5 ] bits in the St atus Regi ster to “1, ” but it cannot clea r the m to “0 .” Issu ing t his com m and
clears those bits to “0.”
90 Read Identifier This command puts the device into the read -identifier mode so that reading the device will output
the manufacturer/d evice code s or block-lock sta tus. Se e Section 10.1.2, “Read Identifier” on
page 41.
60
Blo ck Lock,
Blo ck U nlock,
Blo ck Lock - D own
Set-Up
This comman d pr ep ar es the C UI fo r block- lock ing changes. If the next c ommand is not Blo c k
Unl ock, Bl ock Lo ck, or Bl ock Lock-Down, the n the C UI wil l set both t he program and er ase-Statu s
Register bits to indicate a command-sequence error . See Section 11.0, “ Secur ity M ode s” on
page 49.
01 Lock-Block If the previous command was Lock Set-Up, the CUI will latch the address and lock the block
indicated on the address pins. (See Section 11.1)
2F Lock-Down If the previ ous co m m and was a Loc k- Down Set-Up com mand, th e C UI will latch the addre ss and
lock- down th e bloc k in dicated on t he address pins. (See Section 11.1)
98 CFI Query This command puts the device into the CFI-Query mode so that reading the device will output
Common Flash Interface information. See S ec ti o n 10. 1 . 3 and Appendix C, “Common Flash
Interface”.
C0 Protection
Program
Set-Up
This is a tw o- cycle com m and . The firs t cycle pr epa r es the C UI for a prog ra m operatio n to the
prot ectio n r egister. The sec ond cycle lat ches ad dr esse s and d at a informat ion and initiates th e
WSM to execute the Protection P rogr am algor ithm to the p rotection r egister . The f lash output s
Status Register data when CE# or OE# is toggled. A Read Array command is required after
programming t o read array data. See Section 11.5.
10 Alt. Prog Set-Up Operates the same as Program Set-up co m m and. (S ee 0x 40/Program Set- U p)
00 Invalid/
Reserved Unas signed commands should not be used. I ntel reserves the righ t to re define these codes for
future functions.
Note: See Append ix A, “Write State Machine States” for mode transi tion information.
Intel® Advanced + Boot Block Flash Memo ry (C3 )
May 2005 Intel® Advanced+ Bo ot Block Flash Memory (C3) Datasheet
48 Order Numbe r: 290645 , Revision: 023
Tab le 24. Status Register Bit Definition
WSMS ESS ES PS VPPS PSS BLS R
76543210
NOTES:
SR[7] WRITE STATE MACHINE STAT US (WSMS)
1= Ready
0= Busy
Before checking program or erase- status bits, check the Write
State Mach ine bit fi r s t to determi ne Word Program or Bl ock
Er ase co m pleti on.
SR[6] = ERASE-SUSPEND ST ATUS (ESS)
1 = Erase Suspended
0 = Erase In Progress/Completed
When Erase Suspend is issued, WSM halts execution and sets
both WSMS and ESS bits to “1.” ESS bit remains set to “1” until
an Erase Resume command is issued.
SR[5] = ERASE ST ATUS (ES)
1 = Er ror I n Block Eras e
0 = Successful Block Er ase
When this bit is set to “1,” WSM ha s applied the maximum
num ber of erase pulse s to th e block and is stil l unable to ver if y
s ucces sf ul block erasure .
SR[4] = PROGRAM STATUS (PS)
1 = Error in Programmi ng
0 = Successful Programming When this bit is set to “1,” WSM has attempted but failed to
progr am a wor d/byte.
SR[3] = VPP STATUS (VPPS )
1= V
PP Low Detect, Operation Abort
0= V
PP OK
The VPP status bit does not provide continuous indication of
VPP level. The WSM interrogates VPP level only after the
Program or Erase command sequences have been entered
and informs the system if VPP has not been switched on. The
VPP is also che cked before the operatio n is veri fied by the
WSM. The V PP status bit is not guaranteed to report accurate
feedback be tween VPPLK and VPP1Min.
SR[2] = PROGRAM SUSPEND STATUS (PSS)
1 = Pr og ram Sus pe nded
0 = Program in Progress/Com pleted
When Program Suspend is issued, WSM halts execution and
sets both WSMS and PSS bits to “1.” PSS bit remains set to “1”
until a Pr ogram Resume co m mand is i ssued .
SR[1] = BLOCK LOCK S TATUS
1 = Prog/E r ase attemp t ed on a locked bloc k; Op er ation
aborted.
0 = No operation to locked blocks
If a Pr ogram or E rase operat ion is atte m pted to one of the
locke d blocks, thi s bit is se t by the WSM. The oper ation
s pecifi ed is aborte d and the de vice is r eturn ed to re ad status
mode.
SR[0] = RESERVED FOR FUTURE ENHANCEMEN TS (R) This bit is re served for future us e and sh ould be mask ed out
whe n poll ing th e Stat us Re gi st er.
Note: A Command-Sequence Error is indicated when SR[4], SR[5], and SR[7] are set.
Intel® Advanced+ Boot Bloc k Flash Memory (C3)
Datasheet I ntel® Advanced+ B oot Block Flash Mem ory (C3) M ay 2005
Order Number: 290645, Revisio n: 023 49
11.0 Security Modes
11.1 Flexible Block Locking
The Intel® Advanced+ Boot Block Flash Memory (C3) device offers an instant, individual block-
locking scheme that allows any blo ck to be lock ed or unlocked with no lat enc y, enabling in st ant
code a nd dat a protectio n.
This locking scheme offers two levels of protection. The firs t level allows s oftware-only cont rol of
block locki ng (us eful for data blocks that change freq uently), whil e the second level requires
hardware interaction before loc king can be changed (use ful for code blocks tha t ch ange
infrequently).
The fol lowing sect ions will dis cuss th e operat ion of the lockin g syst em. The term “ state [ab c]” will
be us ed to speci fy locki ng states; for examp le, “stat e [001],” where a = value of WP#, b = b it D1 of
the Block Lock Status Regi s ter, and c = bit D0 of the Block L ock Status Register. Figure 14,
“Block Locki ng S ta te Diag ram” on page 49 displays all of the po ssible loc k ing s tates.
Figure 14. Block Locking State Diagram
[X00]
[X01]
Power-Up/Reset
Unlocked
Locked
[011]
[111] [110]
Locked-
Down4,5
Software
Locked
[011]
Hardware
Locked5
Unlocked
WP# Hardware Control
Notes: 1. [a, b,c] represents [WP#, D1, D0]. X = Don’t Care.
2. D 1 indicat es block Loc k-dow n stat us. D1 = ‘0’, Loc k -dow n has not been is sued t o
t hi s bloc k . D1 = ‘1’, Loc k - down has been is sued t o t his bloc k.
3. D 0 indicat es block lock st atus. D 0 = ‘0’, block is unloc k ed. D 0 = ‘1’, bloc k is loc ked.
4. Loc k ed-dow n = H ar dwar e + Soft ware loc ked.
5. [ 011] s t at es should be t rac k ed by syst em software to determine difference
bet ween Hardw are Loc ked and Loc k ed -D ow n s t at es .
Software B lock Lock (0x60/0x01) or Software Block Unlock (0x60/0xD0)
Software B lock Lock-Down (0x60/0x2F)
WP# hardw are control
Intel® Advanced + Boot Block Flash Memo ry (C3 )
May 2005 Intel® Advanced+ Bo ot Block Flash Memory (C3) Datasheet
50 Order Numbe r: 290645 , Revision: 023
11.1.1 Locking Operation
The lock ing s tatus of ea ch block can be set to Locked, Unloc ked, or Lock-Down, each of which
will be described in the following sections. See Fig u r e 1 4, “Bl o ck Lo ck in g Stat e D ia g r am” on
page 49 and Figure 21, “Locking Operations Flowchart” on page 60.
The following paragraph conci s ely sum mar izes the loc k ing functiona lity.
11.1.1.1 Locke d Sta te
The default state of all blocks upon power-up or reset is locked (s tates [001] or [101]). Locked
blocks are fully protected from alteration. Any Program or Erase operations attempted on a locked
block will return an error on bit SR[1]. The state of a locked block can be changed to Unlocked or
Lock Down using the appropriate software commands. An Unlocked block can be locked by
writing the Lock command sequence, 0x60 followed by 0x01.
11. 1.1.2 Unlocked Stat e
Unlocked block s (sta tes [000], [100], [110]) can be programm ed or eras ed. All unlocked bl ocks
return to the Locked state when the device is reset or powered down. The status of an unlocked
block can be changed to Locked or Locked Down us ing the appropri ate so ftware commands. A
Loc ked block can be unlocked by writing the Unl ock command sequence, 0 x60 followed by 0xD0.
11.1.1.3 Lock- Down State
Blocks that are Locked-Down (state [011]) are protected from Program and Erase operations (just
like Locke d blocks), but thei r protec tio n status ca nnot be ch anged using sof tware command s alon e.
A Lock ed or Unloc ked block can be Locked Down by writing t he Lock-Down c ommand seque nce,
0x60 fol lowed by 0x2F. Locked -Down blocks revert to the Lock ed state when the device is reset or
powere d down.
The Lock-Down function depends on the WP# input pin. When WP# = 0, blocks in Lock Down
[ 011] are protected from program, erase, and lock sta tus changes. Whe n WP# = 1, the Lock-Down
f unct ion is disable d ([111]), and Locked -Down bloc ks can be indi vidually unlocked by softwa re
command to the [110] state, where they can be erased and programmed. These blocks can then be
relocked [111] and unlocked [110] as required while WP# remains high. When WP# goes low,
blocks that were previously Locked Down return to the Lock-Down state [011], regardless of any
cha nges m ade while WP# was high. De vice reset or power-down rese ts al l blocks, incl uding those
in Lock-Down, to Locked state.
11.2 Re ading Bl ock- Lock Status
The Lock stat us of each block c an be read in read -identifier mode of the device by issuing the read-
identifie r comma nd (0x90). Subsequent reads at Bloc k Address + 0x00002 wil l output the Loc k
st at us of that block . The Lock stat us is repre sented by DQ0 and DQ1:
•DQ0 indicates the Block Lock/Unlock status and is set by the Lock command and cleared by
t h e U n lock comm and. It is also au tomaticall y set when entering Lock Down.
•DQ1 indicate s Loc k-Down status and is set by the Lock -Down c ommand. It c annot be cleared
by software —only by device reset or power-down.
See Table 21, “Device Identification Codes” on page 42 for block-status information.
Intel® Advanced+ Boot Bloc k Flash Memory (C3)
Datasheet I ntel® Advanced+ B oot Block Flash Mem ory (C3) M ay 2005
Order Number: 290645, Revisio n: 023 51
11 .3 L oc kin g Op er at ion s du ri ng Eras e Susp en d
Change s to bloc k-lock status ca n be perf ormed during an erase-suspend by using the standa rd
locking command sequences to Unl ock, Lock, or Lock Down a block. This operation is useful in
the ca s e when another block nee ds to be updated while an Erase opera tion is in progress.
To change bl ock lo cking du ring an Eras e opera tion, fi rst i ssue t he Erase Suspe nd comma nd (0xB0),
and then check the Status Regist er until it indica tes that the Er as e ope ration has bee n suspended.
Next, write the prefe rred Loc k command sequence t o a block and the Lock st at us will be cha nged.
After compl et ing an y prefe rred Loc k, Re ad, or Pro gram operations, resum e the Era se opera ti on
wi th th e Er a se Re su me co mma n d (0 xD0 ) .
If a block is Lo cke d or Loc ked Down during a Sus pended Erase of the s ame block, the locking
status bits will be changed immediately. But when the Erase is resumed, the Erase operation will
complete.
Locking operation s cannot be per f orm ed duri ng a Program Suspend. Re fer to Appendix A, “Write
Stat e M ac h ine Stat e s ” on p ag e 54 for detailed inform ation on which comm ands are val id during
Era s e Su s p en d .
11.4 Status Register Error Checking
Using nes te d-locking or progra m-c om ma nd s eque nces during Era se Su sp end ca n introduce
ambi guity into Status Regist er results .
Sin ce locking cha nges are performed using a two-cycl e co mmand sequence, for example , 0x60
followe d by 0x01 to l ock a block. Following t he Block Lock, Block Unlock, or Block Lock-Down
Setup c ommand (0x60) with an invali d command wil l produce a Lo ck-Command e rror (S R[4] and
SR[5] will be set to 1) in the S tatus Regis ter. If a Lock-Co mmand error oc curs during an Erase
Suspend, SR[4] and SR[5] will be set to 1 and will rem ain at 1 after the Era se is res um ed. Whe n
Erase is compl ete, any possibl e e rror during the Erase cannot be detect ed by the Status Regist er
because of the previous Loc k-Command error.
A simila r situation happ ens if an error occurs during a Program-Operation error ne s ted within an
Era s e Su s p en d .
11.5 128-Bit Protection Register
The C3 de vice architec ture includes a 128-bit protecti on register than can be used to increase the
security of a syste m desi gn. For exam ple, the number c ontained in the prote ction register can be
used to “mat ch” the flash com ponent with other s ystem components, such as the CPU or ASIC,
preventing device substitution. Application note, AP-657 Designing with the Advanced+ Boot
Bloc k Fl ash Memory Ar chitecture, contains additional application information.
The 128 bits of t he protec tion register are divided int o two 64 -bit seg me nts . One of the s egments is
program m ed at the Int el fact ory with a unique 64-bit number, whic h is uncha ngeable. The other
seg ment is left bl ank for c us tom er designs to pro g ram, as pr efe rred. Once the customer segment is
program m ed, it can be locked to prevent further program ming.
Intel® Advanced + Boot Block Flash Memo ry (C3 )
May 2005 Intel® Advanced+ Bo ot Block Flash Memory (C3) Datasheet
52 Order Numbe r: 290645 , Revision: 023
11.5.1 Reading the Protection Register
The protection regis ter is read in the Rea d-Identifier mode. T he device is switched to this mode by
is suing the Rea d Identifi er comman d (0x90). Once in this mode , read cycles from add resses shown
in Figure 15, “ P rotecti on Register Mappi ng” retrieve the specified information. To return to Read-
Arr ay mode, is s ue the Rea d Ar ray co mmand (0xF F) .
11.5.2 Programming the Protection Register
The pr otection regis te r bits are program me d us ing the two-cycl e Protection Pro gram com ma nd.
The 64-bit number is programmed 16 bits at a time. First, issue the Protection Program Setup
com ma nd, 0xC0. The next write to the de vice will latch in addre s s and data and program the
specif ied lo catio n. Th e allo w abl e ad d r esses ar e listed in Table 21, “Device Identification Codes”
on pag e 42 . See Figure 22, “Protection Register Programming Flowchart” on page 61. A ttempting
to program to a previous ly locked protectio n register seg ment will result in a Status Register error
(Pr ogram Err or bit SR[4] and Lock Error bit SR[1] wil l be set to 1).
Note: Do not attempt to address Protection Program comm ands outside the defined protection register
addre s s space; status register can be indet erminate.
11.5 .3 Lock ing the Prote ction Regis ter
The us er-pr ogrammable segme nt of the protection regist er i s l ockable by programming bit 1 of the
PR-LOCK location to 0. See Figure 15, “Prot ec ti on Regi s ter Mappi ng” on pa ge 52. Bit 0 of this
location is programmed to 0 at the Intel factory to protect the unique de vice numbe r. This bi t is set
using the Protection Program command to program 0xFFFD to the PR-LOCK location. After these
bits have been programmed, no further cha nges ca n be made to the value s sto red in the prot ec tion
r egister. Prot ectio n Program com mands to a locked se ction wil l result in a Status Registe r er r or
( Pr ogram Error bit S R[4] and Lock Error bit S R[1] will be set to 1). Protection regi st er lockout
stat e is n o t r evers ible .
11.6 VPP Program and Erase Voltages
The C3 device provides in-system programming and erase in the 1.65 V–3.6 V range. For fa st
pr oduc tion p rogramming, 12 V progr ammi ng can be us ed. See F igure 16, “Example P ower Supply
Configurations” on page 53 .
Figu re 15 . Prot ect i on Reg is te r Ma p pi ng
0
x88
0
x85
64-bi t Segment
(User-Programmable)
0
x84
0
x81
0
x80 PR Loc k R egis t er 0
64-bi t Segment
(Intel Factory-Programmed)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
128- Bit Pro t ection Regis ter 0
Intel® Advanced+ Boot Bloc k Flash Memory (C3)
Datasheet I ntel® Advanced+ B oot Block Flash Mem ory (C3) M ay 2005
Order Number: 290645, Revisio n: 023 53
11.6.1 Program Pro tection
In addi ti on to th e flexi ble block lockin g, the VPP prog ramming vo ltage can be he ld low for absol ute
hardware write protection of all blocks in the flash device. When VPP is belo w or equa l to VPPLK,
any Pr ogram or Era se operat ion will result in an error, promptin g the correspond ing S ta tus Regis ter
bit ( S R[ 3]) to be set.
0645_06
Note:
1.A r esistor can be used if the V CC supply can sink adequate current based on resistor value. See AP-657
Designing with the Advanced+ Boot Block Flash Memory Architecture for details.
Figure 16. E xample P owe r Su pply Conf iguration s
V
CC
V
PP
12 V Fast Pr og r amm ing
Absolute Write Protection With V
PP
≤
V
PPLK
System Supply
12 V Supply
10
≤
K
Ω
V
CC
V
PP
System Supply
12 V Supply
Low Voltage and 12 V Fast Programming
V
CC
V
PP
System Supply
Prot#
(Logic Signal)
V
CC
V
PP
System Supply
Low-Voltage Programming
Low-Voltage Programming
Absolute Write Protection via Logic Signal
(Note 1)
Intel® Advanced + Boot Block Flash Memo ry (C3 )
May 2005 Intel® Advanced+ Bo ot Block Flash Memory (C3) Datasheet
54 Order Numbe r: 290645 , Revision: 023
Appendix A Write State Machine States
Table 25 and Table 26 show the Write State Mac h ine co mmand sta te trans itions bas ed on incomi ng
commands.
Table 25. Write State M ach ine States
Command Input (and Next State)
Current State SR.7 Data
When
Read Read Array
(FFH) Program
Setup (10/
40H)
Erase
Setup
(20H)
Erase
Confirm
(D0H)
Prog/Ers
Suspend
(B0H)
Prog/Ers
Resume
(D0)
Read
Status
(70H)
Clear
Status
(50H)
Read Arr a y “1” Array Read Array Prog. Setup Ers. Setup Read Array Read Sts. Read Array
Read Status “1” Status Read Array Prog. Setup Ers. Setup Read Array Read Sts. Read Array
Read Config. “1” Config Read Array Prog. Setup Ers. Setup Read Array Read Sts. Read Array
Read Query “1” CFI Read Array Prog. Setup Ers. Setup Read Array Read Sts. Read Array
Lock Setup “1” Status Lock Command Error Lock (Done) Lock
Cmd. Error Lock
(Done) Lock Cmd. Error
Lock Cmd. Error “1” Status Read Arr a y Prog. Setup Ers. Setup Read Array Read Sts. Read Array
Lock Oper. (Done) “1” Status Read Array Prog. Setup Ers. Setup Read Array Read Sts. Read Array
Prot. Prog. Setup “1” Status Protection Register Program
Prot. Prog.
(Not Done) “0” Status Protection Register Program (Not Done)
Prot. Prog. (Done) “1” Status Read Arra y Prog. Setup Ers. Setup Read Array Read Sts. Read Array
Prog. Setup “1” Status Program
Program (Not Done) “0” Status Program (Not Done) Prog. Sus.
Status Program (Not Done)
Prog. Susp. Status “ 1 ” Status Prog. Sus.
Read Array Program Susp end
Read Array Prog. (Not
Done) Prog. Sus.
Rd. Array Program
(Not Done) Prog. Sus.
Status Prog. Sus.
Rd. Array
Prog. Susp. Read
Array “1” Array Prog. Sus.
Read Array Program Susp end
Read Array Prog. (Not
Done) Prog. Sus.
Rd. Array Program
(Not Done) Prog. Sus.
Status Prog. Sus.
Rd. Array
Prog. Susp. Read
Config “1” Config Prog. Sus.
Read Array Program Susp end
Read Array Prog. (Not
Done) Prog. Sus.
Rd. Array Program
(Not Done) Prog. Sus.
Status Prog. Sus.
Rd. Array
Prog. Susp. Read
Query “1” CFI Prog. Sus.
Read Array Program Susp end
Read Array Prog. (Not
Done) Prog. Sus.
Rd. Array Program
(Not Done) Prog. Sus.
Status Prog. Sus.
Rd. Array
Program (Done) “1” Status Read Array Prog. Setup Ers. Setup Read Array Read Status Read Array
Erase Setup “1” Status Erase Command Error Erase
(Not Done) Erase Cmd.
Error Erase
(Not Done) Erase Command Error
Erase Cmd. Error “1” Status Read Arr ay Prog. Setup Ers. Setup Read Array Read Status Read Array
Erase (Not Done) “0” Status Erase (Not Done) Erase Sus.
Status Erase (Not Done)
Ers. Susp. Status “1” Status Erase Sus.
Read Array Prog. Setup Ers. Sus.
Rd. Array Erase Ers. Sus. Rd.
Array Erase Erase Sus.
Status Ers. Sus.
Rd. Array
Erase Susp. Array “1” Array Erase Sus.
Read Array Prog. Setup Ers. Sus.
Rd. Array Erase Ers. Sus. Rd.
Array Erase Erase Sus.
Status Ers. Sus.
Rd. Array
Ers. Susp. Read
Config “1” Config Erase Sus.
Read Array Prog. Setup Ers. Sus.
Rd. Array Erase Ers. Sus. Rd.
Array Erase Erase Sus.
Status Ers. Sus.
Rd. Array
Ers. Susp. Read
Query “1” CFI Erase Sus.
Read Array Prog. Setup Ers. Sus.
Rd. Array Erase Ers. Sus. Rd.
Array Erase Erase Sus.
Status Ers. Sus.
Rd. Array
Erase (Done) “1” Status Read Array Prog. Setup Ers. Setup Read Array Read Sts. Read Array
Intel® Advanced+ Boot Bloc k Flash Memory (C3)
Datasheet I ntel® Advanced+ B oot Block Flash Mem ory (C3) M ay 2005
Order Number: 290645, Revisio n: 023 55
Table 26. Write State Machine State s, Continued
Command Input (and Next State)
Current State Read Config
(90H) Read Query
(98H) Lock Setup
(60H) Prot. Prog. Setup
(C0H) Lock Confirm
(01H) Lock Down
Confirm
(2FH) Unlock Confirm
(D0H)
Read Array Read Config. Read Query Lock Setup Prot. Prog. Setup Read Array
Read Status Read Config. Read Query Lock Setup Prot. Prog. Setup Read Array
Read Config. Read Config. Read Query Lock Setup Prot. Prog. Setup Read Array
Read Query Read Config. Read Query Lock Setup Prot. Prog. Setup Read Array
Lock Setup Locking Command Error Lock Operation (Done)
Lock Cmd. Error Read Config. Read Query Lock Setup Prot. Prog. Setup Read Array
Lock Oper. (Done) Read Config. Read Query Lock Setup P rot. Prog. Setup Read Array
Prot. Prog. Setup Protection Register Program
Prot. Prog.
(Not Done) Protection Register Program (Not Done)
Prot. Prog. (Done) Read Config. Read Query Lock Setup Prot. Prog. Setup Read Array
Prog. Setup Program
Program
(Not Done) Program (Not Done)
Prog. Susp. Status Prog. S usp. Read
Config. Prog. S usp. Read
Query Program Suspend Read Array Program
(Not Done)
Prog. Susp. Read
Array Prog. Susp. Rea d
Config. Prog. S usp. Read
Query Program Suspend Read Array Program
(Not Done)
Prog. Susp. Read
Config. Prog. Susp. Rea d
Config. Prog. S usp. Read
Query Program Suspend Read Array Program
(Not Done)
Prog. Susp. Read
Query. Prog. Susp. Rea d
Config. Prog. S usp. Read
Query Program Suspend Read Array Program
(Not Done)
Program
(Done) Read Config. Read Query Lock Setup Prot. Prog. Setup Read Array
Erase
Setup Erase Command Error Erase
(Not Done)
Erase Cmd. Error Read Config. Read Query Lock Setup Prot. Prog. Setup Read Array
Erase
(Not Done) Erase (Not Done)
Erase Susp.
Status Ers. Susp. Read
Config. Erase Suspend
Read Query Lock Setup Erase Suspend Read Array Erase
(Not Done)
Erase Suspend
Array Ers. Susp. Read
Config. Erase Suspend
Read Query Lock Setup Erase Suspend Read Array Erase
(Not Done)
Eras Sus. Read
Config Erase Suspend
Read Config. Erase Suspend
Read Query Lock Setup Erase Suspend Read Array Erase
(Not Done)
Eras Sus. Read
Query Erase Suspend
Read Config. Erase Suspend
Read Query Lock Setup Erase Suspend Read Array Erase
(Not Done)
Ers.(Done) Read Config. Read Query Lock Setup Prot. Prog. Setup Read Array
Intel® Advanced + Boot Block Flash Memo ry (C3 )
May 2005 Intel® Advanced+ Bo ot Block Flash Memory (C3) Datasheet
56 Order Numbe r: 290645 , Revision: 023
Appendix B Flow Charts
Figu re 17 . Word Progra m Fl owcha rt
Program
Suspend
Loop
Start
Write 0x40,
Word Address
Write Data,
Word Address
Read Status
Register
SR[7] =
Full S t at u s
Check
(if d esi red)
Program
Complete
Suspend?
1
0
No
Yes
WORD PROGRAM PROCEDURE
Repeat for subsequen t Word Program operations.
Full Status Register check can be done after each program, or
after a sequence of program operations.
Write 0xFF after the last operation to set to the Read Array
state.
Comments
Bus
Operation Command
Data = 0x4 0
Addr = Location to program
Write Program
Setup
Data = Data to program
Addr = Location to program
Write Data
Status register data : Toggle CE# or
OE# to update Status Register
Read None
Check S R[7 ]
1 = W SM Ready
0 = W SM Busy
Idle None
(S etu p)
(Con firm)
FULL S TATUS CHE CK P ROCEDURE
Read Status
Register
Program
Successful
SR[3] =
SR[1] =
0
0
SR[4] =
0
1
1
1
VPP Ra n g e
Error
Device
Protect Error
Program
Error
SR[3] MUST be cleared be fo re the W rite State Machine will
all ow furt her progra m attempts.
If an error is detected, clear the Status Register be fore
continuing operations - only the Clear Staus Register
command clears the St at us Register error bits.
Idle
Idle
Bus
Operation
None
None
Command
Check S R[3 ]:
1 = VPP
E rro r
Check S R[4 ]:
1 = Data Program E rror
Comments
Idle None Ch e ck S R[1 ]:
1 = Block locked; operation aborted
Intel® Advanced+ Boot Bloc k Flash Memory (C3)
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Order Number: 290645, Revisio n: 023 57
Figure 18. Program S usp end / Resume Flowcha rt
Read Status
Register
SR[7] =
SR[2] =
Read A rray
Data
Program
Completed
Done
Reading
Program
Resumed
Read A rray
Data
0
No
0
Yes
1
1
PROGRAM SUS PEND / RESUME PROCEDURE
Write Program
Resume Data = 0xD0
Addr = Any address
Bus
Operation Command Comments
Write Program
Suspend Data = 0xB0
Add r = Any address
Idle None Check SR[ 7]:
1 = WSM ready
0 = WSM busy
Idle None Check SR[ 2]:
1 = Program suspended
0 = Program completed
Write Read
Array Data = 0xFF
Add r = Any address
Read None Read array data from block other than
the on e be ing programme d
Read None
Status register data
Toggle CE# or OE# to update Status
register
Addr = Any address
Write 0xFF (Read Array)
Write 0xD0
Any Address (Program Resume)
Write 0xFF (Read
Array)
Write Read
Status Data = 0x70
Add r = Any address
Start
Write 0xB0
Any Address (Program Suspend)
W rite 0x70
Any Address (Read Status)
Intel® Advanced + Boot Block Flash Memo ry (C3 )
May 2005 Intel® Advanced+ Bo ot Block Flash Memory (C3) Datasheet
58 Order Numbe r: 290645 , Revision: 023
Figure 19. Erase Suspe nd / Resume Flow char t
Erase
Completed
Read Array
Data
0
0
1
1
Start
Read Status
Register
SR[7] =
SR[6] =
Erase
Resumed
Done
Reading
Write
Write
Idle
Idle
Write
Erase
Suspend
Read Array
or Program
None
None
Program
Resume
Data = 0xB0
Addr = Any address
Data = 0xFF or 0x40
Addr = Any address
Che ck SR[7]:
1 = WSM ready
0 = WSM busy
Che ck SR[6]:
1 = Erase suspended
0 = Erase completed
Data = 0xD0
Addr = Any address
Bus
Operation Command Comments
Read None Status Register data. Toggle CE# or
OE# to u p da te Sta tus register;
Addr = Any Address
Read or
Write None Read array or program data from/to
block other than the one being erased
E RA SE SUSPEND / RESUME PRO C EDURE
Write 0x70,
Any Address
(Read Status)
Write 0xB0,
Any Address
(E rase Suspen d)
Write 0xD0,
Any Address
(
E rase Resume )
Write 0xFF
(Re ad A rray)
Write Read
Status Data = 0x70
Addr = Any address
R ea d Array
Data
Write 0xFF
0
(Read Array)
1
Intel® Advanced+ Boot Bloc k Flash Memory (C3)
Datasheet I ntel® Advanced+ B oot Block Flash Mem ory (C3) M ay 2005
Order Number: 290645, Revisio n: 023 59
Figure 20. Block Erase Flowchart
Start
FULL E RASE STATUS CHECK PRO CE DURE
Repe at for subseq ue nt block erasures.
Full Status re gister check can b e do ne after each block erase
or after a seque nce of block erasures.
Write 0xFF after the last operation to enter read array mode.
SR[1,3] must be cleared before the Write State Machine will
allow further erase attempts.
Only the Clear Status Register command clears SR[1, 3, 4, 5].
If an error is detected, clear the Status register before
attempti ng an e rase ret ry or ot her e rror recovery .
No
Suspend
Erase
1
0
0
0
1
1,1
1
1
0Yes
Suspend
Erase
Loop
0
W rite 0x20,
Block Address
W rite 0xD0,
Block Address
Read Status
Register
SR[7] =
Full E ras e
Statu s Check
(if desired)
Block Erase
Complete
Read Status
Register
Block Erase
Successful
SR[1] = Block Locked
Error
BLOCK ERASE PR OCEDUR E
Bus
Operation Command Comments
Write Block
Erase
Setup
Data = 0x20
Ad dr = Block to be erased (BA)
Write Erase
Confirm Data = 0xD0
Ad dr = Block to be erased (BA)
Read None Statu s Register data . Togg le CE# or
OE# to update Status register data
Idle None Check SR[7]:
1 = WSM ready
0 = WSM busy
Bus
Operation Command Comments
SR[3] = V
PP
Rang e
Error
SR[4,5] = Command
Sequence Error
SR[5] = Block Era se
Error
Idle None Check SR[3]:
1 = V
PP
Range Error
Idle None Check SR[4,5]:
Both 1 = Command Sequence Error
Idle None Check SR[5]:
1 = Block Erase Error
Idle None Check SR[1]:
1 = Attempted era se of locked block;
erase aborted.
(Block Eras e)
(Erase Confirm)
Intel® Advanced + Boot Block Flash Memo ry (C3 )
May 2005 Intel® Advanced+ Bo ot Block Flash Memory (C3) Datasheet
60 Order Numbe r: 290645 , Revision: 023
Figure 21. Locking Op erati on s Flowch art
No
Start
Write 0x60,
Block Address
Write 0x90
Read Block
Lock Status
Locking
Change?
Lock Change
Complete
Write either
0x01/0xD0/0x2F,
Block Address
Write 0xFF
Any Address
Yes
Write
Write
Write
(Optional)
Read
(Optional)
Idle
(Optional)
Write
Lock
Setup
Lock,
Unlock, or
Lock-Down
Confirm
Read
Device ID
Block Lock
Status
None
Read
Array
Data = 0x60
Addr = Any Ad dress
Data = 0x0 1 (Block Lo ck)
0xD0 (B l ock Unlock)
0x2F (Lo ck-Down Block)
Addr = B lo ck t o lock/unlock/lo ck -d own
Data = 0x90
Addr = Any Ad dress
Block Lock status data
Addr = Block address + offset 2
Confirm locking chan ge o n D[1,0] .
Data = 0xFF
Addr = Any add ress
Bus
Operation Command Comments
LOCKI NG OPERATIONS PROCE DURE
(Lock Confirm)
(Read Device ID)
(Read Array)
Optional
(Lock Setup)
Intel® Advanced+ Boot Bloc k Flash Memory (C3)
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Order Number: 290645, Revisio n: 023 61
Fig ure 22 . P rot ection R egi s te r Pr ogra mm i ng Flowchart
FULL STATUS CHECK PROCE DURE
Program Protection Register operation addresses must be
within the Protection Register address space. Addresses
outside th is space wi ll ret urn an error.
Repea t f or subsequent p rogramming operations.
Full Status Register check can be done after each program, or
after a sequence o f p rogram operations.
Write 0xFF after the last operation to set Read Array state.
SR[3] must be cleared before the Write State Machine will
allow further prog ra m attempts.
Only the Clear Staus Register command clears SR[1, 3, 4 ].
If an error is detected, clear the Status register before
att empting a program retry or othe r error recov ery.
1
0
1
1
PROTE CTI ON REGIS TER PROGRAMMING PROCE DURE
Start
Write 0xC0,
PR Address
Write PR
Address & Data
Read Status
Register
SR[7] =
Full Status
Check
(if d es ired)
Program
Complete
Read Status
Register Data
Program
Successful
SR[3], SR[4] = V
PP
Range Error
Program E rror
Register Locked;
Program Aborted
Idle
Idle
Bus
Operation
None
None
Command
Check SR[1 ], SR[3], SR[4]:
0,1,1 = V
PP
Range Error
Check SR[1 ], SR[3], SR[4]:
0,0,1 = Programming Error
Comments
Write
Write
Idle
Program
PR Setu p
Protection
Program
None
Data = 0xC0
Addr = First Lo ca tion to Program
Data = Data to P rog ram
Addr = Location to Program
Check SR[7 ]:
1 = WS M Ready
0 = WS M Busy
Bus
Operation Command Comments
Read None Status Register Data. Toggle CE# or
OE# to Update Status Register Data
Idle None Check SR[1 ], SR[3], SR[4]:
1,0,1 = Block locked; operation aborted
(Program Setup)
(Confirm Data)
0
0
SR[3], SR[4] =
0
SR[3], SR[4] =
1
Intel® Advanced + Boot Block Flash Memo ry (C3 )
May 2005 Intel® Advanced+ Bo ot Block Flash Memory (C3) Datasheet
62 Order Numbe r: 290645 , Revision: 023
Appendix C Common Flash Interface
This appendix define s the da ta structure or “data base” return ed by the Common Flash Inte rfac e
( CFI) Query co mmand. System softwa re should parse this structure to gain cri ti ca l information
suc h as block size, dens ity, x8/x16, a nd ele ct rical speci f ications. Once this informati on has bee n
ob ta ined, the software detect s whi ch comm and sets to use to enable flash writes, block erases, and
otherwise control the flash component. The Query is part of an overall specification for multiple
com ma nd s et a nd cont rol interface descri ptions calle d Common F la s h Interface, or CFI.
C.1 Query Structure Output
The Query dat ab as e allows s ys te m software to obtain information for controlling the fl ash device.
This section describes the device’s CFI-compliant interface that allows access to Query data.
Query da ta are presented on the lowest -order data outputs (DQ0-DQ7) only. The numerical of fs et
v al ue is the addre s s re lative to the ma ximum bus width su pported by the dev ice . On this fam ily of
devices, th e Que r y table de vice starti ng address i s a 0x10, which is a word address for x16 devic es .
For a word-wide (x16) device, the first two Query -structure bytes , ASCII “Q” and “R,” appea r on
the low byte a t word addresses 0x10 an d 0x11. This CFI-comp liant dev ice outputs 0x00 dat a on
upper bytes. The device outputs ASCII “Q” in the low byte (DQ0-DQ7) and 0x00 in the high byte
(DQ8-DQ15).
At Query ad dres s es containi ng two or more bytes of inform ation, the leas t-significant data byte is
p resented at the lower address, and the most-s ignif ica nt data byte is presented at t h e higher address.
For tabl es in this appendix, address es and data are re presented in hexadecima l notation, so the “h”
suffix has been dropped. In addit ion, since the uppe r byte of word-wide devices is al ways “0x00,”
the lea ding “00” has bee n dropped from the table nota tion and only the lower byte value is shown.
Any x16 device outputs can be assum ed to have 0x00 on the upper byte in this mode.
Table 27. Sum mary of Qu ery Struc ture Ou tput as a Function of Devi ce and Mode
Device Hex Offset Hex Code ASCII Va lue
Device Addresses
00010: 51 "Q"
00011: 52 "R"
00012: 59 "Y"
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Order Number: 290645, Revisio n: 023 63
C.2 Query Struc tu re Overview
The Quer y comma nd ca us es the flash component to dis play the Common Flas h Interface (CFI)
Qu er y str u ct u r e or “d at aba s e .” Table 29 summar izes th e struct u r e sub-sections and ad d r ess
locations.
Tabl e 28. Example of Qu ery Structu re Output of x16 Devices
Word Addressing:
Of f set He x Code Value
A[X-0] DQ[16:0]
0x00010 0051 "Q"
0x00011 0052 "R"
0x00012 0059 "Y"
0x00013 P_IDLO PrVendor
0x 0001 4 P_I D HI ID #
0x00015 PLO PrVendor
0x00016 PHI TblAdr
0x00017 A_IDLO AltVendor
0x 0001 8 A_I D HI ID #
... ... ...
Table 29. Query Structure
Offset Sub-Section Name Description1
0x00000 Man ufac tur er Code
0x00001 Device Code
0x(BA+2)2Block S tatus register Block-specific information
0x00004-0xF Reserved Reserved for vendor-specific information
0x00010 CFI query identification
string Comman d set ID and ve ndor data o ffset
0x0001B System interface
information Device timing & voltage information
0x00027 Device geometry definition Flash device layout
P3Primary Intel-specific
Extended Query Table Ve ndor-defined additiona l info rmati on sp ecific to the Prima ry
Vendor Algor ithm
Notes:
1. Ref er t o the Qu ery Stru cture Out p ut se ctio n and of fs et 0x 28 for the det ail ed defi nit ion o f of fse t ad dr ess
as a function of device bus width and mode.
2. BA = Block Address beginning locatio n ( i. e., 0x 0800 0 is block 1’s beg inning locat ion wh en the block
size is 32K-word).
3. Offset 15 defines “P” which points to the Primary Intel-specific Extended Query Table.
Intel® Advanced + Boot Block Flash Memo ry (C3 )
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64 Order Numbe r: 290645 , Revision: 023
C.3 Block Statu s Re gi st er
The Block S tat us Register indicates whet her a n erase opera tion complet ed s uccessfully or whether
a give n block is locked or can be acce s s ed for fla s h program/erase ope rat ions. See Table 30.
Block Era se S tatus (BSR[1] ) al lows sy st em sof tware to determi ne the su ccess of the last block
erase operation. BSR[1] can be used just after power-up to verify that th e VCC supply was not
accidentally rem oved during an erase ope rat ion.
Notes:
1. BA = Bloc k A ddr ess be gi nni ng locat ion (i.e. , 0x 08 00 0 is b lock 1 ’ s beg i nnin g loc at ion w hen the b l ock size
is 32K-word).
Tab le 30. Block Status Register
Offset Length Description Add. Value
0x(BA+2)11
Block Lock Status Register BA+2 --00 or --01
BS R[0] Bl ock lock status
0 = Unlocked
1 = Locked BA +2 (bi t 0): 0 or 1
BS R[1] Block lock-d ow n status
0 = Not locked down
1 = Locked down BA +2 (bi t 1): 0 or 1
BSR[7:2]: Reserved for future use BA+2 (bit 2-7): 0
Intel® Advanced+ Boot Bloc k Flash Memory (C3)
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Order Number: 290645, Revisio n: 023 65
C.4 CFI Query Identification S tring
The Identification String provides verification that the component supports the Common Flash
Interface specification. It also indicates the spec ification version and suppo rted vendor-s pec ified
comma nd set( s). See Table 31.
Table 31. CFI Identification
Of f set Length Des cr ipt ion Add. He x Code Va lu e
0x10 3 Query-unique ASCII string “QRY“ 10:
11:
12:
--51
--52
--59
“Q”
“R”
“Y”
0x13 2 P r imary vendor comm and set and co ntrol interface ID code
16-bit ID code for vendor-specified algorithms 13:
14: --03
--00
0x15 2 Extended Query Table primary algorithm address 15:
16: --35
--00
0x17 2 Alternate vendor command set and control interface ID code
0x0000 m eans no seco nd vendor- specifi ed algorithm exists 17:
18: --00
--00
0x19 2 Secondary algorithm Extended Query Table address
0x0000 means none exists 19:
1A: --00
--00
Intel® Advanced + Boot Block Flash Memo ry (C3 )
May 2005 Intel® Advanced+ Bo ot Block Flash Memory (C3) Datasheet
66 Order Numbe r: 290645 , Revision: 023
Table 32. S ystem Interface Information
C.5 Device Geometry Definition
Table 33. Device Geometry Definition
Off s et Lengt h Descr i ption Ad d. H e x Code Value
0x1B 1 VCC logi c supp ly minimum progr am / erase voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts 1B: --27 2.7 V
0x1C 1 VCC logic supp ly maximum progr am/erase volt age
bits 0–3 BCD 100 mV
bits 4–7 BCD volts 1C: --36 3.6 V
0x1D 1 VPP [pr ogrammin g] supply m inimum progr am/erase volt age
bits 0–3 BCD 100 mV
bits 4–7 HEX volts 1D: --B4 11.4 V
0x1E 1 VPP [progr ammin g] supply maximu m pr ogram/erase volta ge
bits 0–3 BCD 100 mV
bits 4–7 HEX volts 1E: -- C6 12.6 V
0x1F 1 “n” such that typical single wo rd pro gr am time-out =2n µs 1F: --0 5 32 µs
0x20 1 “n” such that typical max. buffer write time-out = 2n µs 20: --0 0 NA
0x 21 1 “n” such that typical block er ase time-out = 2n ms 21: --0A 1 s
0x 22 1 “n” such th at typical full ch ip erase tim e- out = 2n ms 22: --00 NA
0x23 1 “n” such that maximum word program time-out = 2n times typical 23: --04 512µs
0x 24 1 “n” such that maximu m buffer wr it e time- out = 2n times typical 24: --00 NA
0x 25 1 “n” such that maximum bloc k er ase time-out = 2n times typical 25: --03 8s
0x26 1 “n” such that maximum chip erase time-out = 2n times typical 26: --00 NA
Offset Length Description Add. Hex
Code Value
0x27 1 “n” such that device size = 2n in number of bytes 2 7 See T able 34, “Device
Geometry Details” on
page 67
0x28 2 Flash device interface: x8 async
28:00,29:00 x16 async
28:01,29:00 x8/x16 async
28:02,29:00 28:
29: --01
--00 x16
0x2A 2 “n” such that maximum number of bytes in write buffer = 2n2A:
2B: --00
--00 0
0x2C 1
Number of erase block regions within device:
1. x = 0 means no erase blocking; the device erases in “bulk”
2. x specifies the number of device or partition regions
with one or more contiguous same-size erase blocks.
3. Symmetrically blocked partitions have one blocking region
4. Partition size = (total blocks) x (individual block size)
2C: --02 2
0x2D 4 Erase Block Region 1 Information
bits 0–15 = y, y+1 = number of identical-size erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
2D:
2E:
2F:
30:
See T able 34, “Device
Geometry Details” on
page 67
0x2D 14 Erase Block Region 2 Information
bits 0–15 = y, y+1 = number of identical-size erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
31:
32:
33:
34:
See T able 34, “Device
Geometry Details” on
page 67
Intel® Advanced+ Boot Bloc k Flash Memory (C3)
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Order Number: 290645, Revisio n: 023 67
Table 34. Device Geo m etry Details
Address 16 Mbit 32 Mbit 64 Mbit
-B -T -B -T -B -T
0x27 --15 -15 --16 -16 --17 --17
0x28 --01 --01 --01 --01 --01 --01
0x29 --00 --00 --00 -00 -00 -00
0x2A --00 --00 --00 -00 -00 -00
0x2B --00 --00 --00 -00 -00 -00
0x2C --02 --02 --02 --02 --02 --02
0x2D --07 --1E --07 --3E --07 --7E
0x2E --00 --00 --00 -00 -00 -00
0x2F --20 --00 --20 -00 --20 --00
0x30 --00 --01 --00 --01 --00 --01
0x31 --1E --07 --3E --07 --7E --07
0x32 --00 --00 --00 -00 -00 -00
0x33 --00 --20 --00 --20 --00 --20
0x34 --01 --00 --01 --00 --01 --00
Intel® Advanced + Boot Block Flash Memo ry (C3 )
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C.6 Intel-Specific Extended Query Table
Cert ain flash features a nd c omm a nds are optional as s hown in Table 35, “Pri mary-Vend or S pec ifi c
Ext ende d Query” on page 68 . The In te l-sp e cif ic Ext end ed Quer y tab l e s p ecif ies these f eatu r es as
well as other similar types of information.
Table 35. Primar y-Vendor Specific Extended Qu ery
Offset1
P = 0x15 Length Description
(Opt ional Fl as h Feat ur e s an d Co mm an ds) Addre ss Hex Code Value
0x(P+0)
0x(P+1)
0x(P+2) 3Primary e x t ende d query table
Unique ASCII string “PRI” 35:
36:
37:
--50
--52
--49
“P”
“R”
“I”
0x ( P+3) 1 Major version number, AS CII 38: - -3 1 “1”
0x ( P+4) 1 Minor version number, AS CII 39: - -3 0 “0”
0x(P+5)
0x(P+6)
0x(P+7)
0x(P+8) 4
Optional feature and command support (1=yes,
0=no)
bit s 9–31 a re r eser ve d; und efi ne d bit s ar e “0. ” If bi t
31 is “1” then another 31 bit field of optional
featur es foll ows at the end of the bit-3 0 field .
3A:
3B:
3C:
3D:
--66
--00
--00
--00
bit 0 Chip erase supported
bit 1 Suspend erase supported
bit 2 Sus pend progra m supported
bit 3 Lega cy lock/unlock support ed
bit 4 Queued erase supported
bit 5 Instant individual blo ck locking support ed
bit 6 Prot ection bit s supp or ted
bit 7 Page mode read supported
bit 8 Synchronous read supported
bit 0 = 0
bit 1 = 1
bit 2 = 1
bit 3 = 0
bit 4 = 0
bit 5 = 1
bit 6 = 1
bit 7 = 0
bit 8 = 0
No
Yes
Yes
No
No
Yes
Yes
No
No
0x(P+9) 1
Suppor ted fun ctions after suspend: Rea d Array,
Status, Query
Oth er supp or ted operations ar e:
bits 1–7 reserved; undefined bits ar e “0” 3E: --01
bit 0 Pr ogram su pport ed aft er erase susp end bit 0 = 1 Yes
0x(P+A)
0x(P+B) 2Block Status Register mask
bits 2–15 a r e Reser v ed; undefi ned bi t s are “0”
bit 0 Block Lock-Bit Status Register active
bit 1 Bl ock Lo ck-Do w n Bit Status active
3F: --03
40: --00
bit 0 = 1 Yes
bit 1 = 1 Yes
0x(P+C) 1 VCC log ic sup ply highes t perform anc e progr am/
erase voltage
bit s 0–3 BCD value in 100 m V
bit s 4–7 BCD value in volts 41 : --33 3.3 V
0x(P+D) 1 VPP optimum program/erase supply voltage
bit s 0–3 BCD value in 100 m V
bit s 4–7 HEX value i n volts 42: --C0 12.0 V
Notes:
1. The variable P is a pointer which is defined at CFI of fset 0x15 .
Intel® Advanced+ Boot Bloc k Flash Memory (C3)
Datasheet I ntel® Advanced+ B oot Block Flash Mem ory (C3) M ay 2005
Order Number: 290645, Revisio n: 023 69
Table 36. Protection Register Information
Offset1
P = 0x35 Length Description
(Optional Flash Features and Commands) Address Hex
Code Value
0x(P+E) 1 Number of Protection register fields in JEDEC ID space.
“00h,” indicates that 256 prot ectio n bytes are avai la ble 43: --01 01
0x(P+F)
0x(P+10)
(0xP+11)
4
44:
45:
46:
--80
--00
--03
80h
00h
8 byt e
0x(P+12)
Protection Field 1: Protection Description
This field describes user-available One Time Programmable (OTP)
Pr otect ion reg ister byt es. Some a r e pr e-pr ogrammed wi th devi ce-
unique serial numbers. Others are user programmable. Bits 0–15
point to th e Protection registe r Lock byte, the section’ s first byte.
The foll ow ing bytes ar e fact or y pre- pr ogrammed and user-
programmable.
bits 0–7 = Lock/bytes JEDEC-plane physical low address
bits 8–15 = Lock/bytes JE DEC -plane physical high addr ess
bits 16–23 = “ n” such that 2n = factory pre-programmed byte s
bits 24–31 = “ n” such that 2n = user programmable bytes
47: --03 8 byte
0x(P+13) Reserved for future u se 48:
Notes:
1. The var iable P is a point er which is def ined at CFI offset 0x15.
Intel® Advanced + Boot Block Flash Memo ry (C3 )
May 2005 Intel® Advanced+ Bo ot Block Flash Memory (C3) Datasheet
70 Order Numbe r: 290645 , Revision: 023
Appendix D Additional Information
Order Number Document/Tool
297938 3 Volt Advanced+ Boot Block Flash Memory Specification Update
292216 AP-658 De signi ng fo r Upgrade to the Advanced+ Boo t Block Flash Me mory
292215 AP-657 Designi ng wit h the Advanced+ Boot B lock Flash Memory
Architecture
Contact your Intel
Representative Intel® Flash Data Integrator ( Intel® FDI) Software Developer’s Kit
297874 IFDI Interactive: Play with Intel® Flash Data Integrator on Your PC
Notes:
1.C all th e I nte l Lit er ature C ente r at ( 8 00) 548- 4725 t o re quest Int el d oc ume nt atio n. I nte rnat ion al cust om ers
should contact their local Intel or distribution sales office.
2.See the Intel page at ‘http://www.intel.com/design/flash’ for technical documentation and tools.
Intel® Advanced+ Boot Bloc k Flash Memory (C3)
Datasheet I ntel® Advanced+ B oot Block Flash Mem ory (C3) M ay 2005
Order Number: 290645, Revisio n: 023 71
Appen dix E Or dering Information
Figure 23. Compon ent Ord ering Informatio n
Package
TE = 48-Lead TSO P
GT = 48-Ball µBGA* CSP
GE = VF BGA CSP
R C = Easy BGA
PC = Pb F ree Easy BGA
PH = Pb F ree VF BGA
J S = Pb Free TSOP
Product line designator
f or all Intel
®
F lash produc t s
A ccess Speed (n s)
(70, 80, 90, 100, 110)
Product Family
C3 = 3 Volt Adv anc ed+ Boot Bloc
k
V
CC
= 2.7 V–3.6 V
V
PP
= 2.7 V–3.6 V or
11. 4 V–12.6 V
De vice De nsity
640 = x16 (64 Mbit)
320 = x16 (32 Mbit)
160 = x16 (16 Mbit)
800 = x16 (8 Mbit )
T = T o p Bl oc k in g
B = B ot t om Bl oc kin g
Lithography
A = 0. 25 µm
C = 0.18 µm
D = 0.13 µm
T E 2 8 F 3 2 0 C 3 T C 7 0
Intel® Advanced + Boot Block Flash Memo ry (C3 )
May 2005 Intel® Advanced+ Bo ot Block Flash Memory (C3) Datasheet
72 Order Numbe r: 290645 , Revision: 023
Table 37. Product Inform ation Ordering Matr ix
VALID COMBINATIONS (All Extended Temperature)
48-Lead TSOP 48-Ball µBGA* CSP 48-Ball VF BGA Easy BGA
Extended
64 Mbit
Extended
32 Mbit
TE28F320C3TD70
TE28F320C3BD70
TE28F320C3TC70
TE28F320C3BC70
TE28F320C3TC90
TE28F320C3BC90
TE28F320C3TA100
TE28F320C3BA100
TE28F320C3TA110
TE28F320C3BA110
JS28F320C3BD70
JS28F320C3TD70
JS28F320C3BD90
JS28F320C3TD90
GT28F320C3TA100
GT28F320C3BA100
GT28F320C3TA110
GT28F320C3BA110
GE28F320C3TD70
GE28F320C3BD70
GE28F320C3TC70
GE28F320C3BC70
GE28F320C3TC90
GE28F320C3BC90
PH28F320C3BD70
PH28F320C3TD70
PH28F320C3BD90
PH28F320C3TD90
RC28F320C3TD70
RC28F320C3BD70
RC28F320C3TD90
RC28F320C3BD90
RC28F320C3TC90
RC28F320C3BC90
RC28F320C3TA100
RC28F320C3BA100
RC28F320C3TA110
RC28F320C3BA110
PC28F320C3BD70
PC28F320C3TD70
PC28F320C3BD90
PC28F320C3TD90
Extended
16 Mbit
TE28F160C3TD70
TE28F160C3BD70
TE28F160C3TC70
TE28F160C3BC70
TE28F160C3TC80
TE28F160C3BC80
TE28F160C3TC90
TE28F160C3BC90
TE28F160C3TA90
TE28F160C3BA90
TE28F160C3TA110
TE28F160C3BA110
JS28F160C3BD70
JS28F160C3TD70
GT28F160C3TA90
GT28F160C3BA90
GT28F160C3TA110
GT28F160C3BA110
GE28F160C3TD70
GE28F160C3BD70
GE28F160C3TC70
GE28F160C3BC70
GE28F160C3TC80
GE28F160C3BC80
GE28F160C3TC90
GE28F160C3BC90
PH28F160C3BD70
PH28F160C3TD70
RC28F160C3TD70
RC28F160C3BD70
RC28F160C3TC70
RC28F160C3BC70
RC28F160C3TC80
RC28F160C3BC80
RC28F160C3TC90
RC28F160C3BC90
RC28F160C3TA90
RC28F160C3BA90
RC28F160C3TA110
RC28F160C3BA110
PC28F160C3BD70
PC28F160C3TD70
Extended
8 Mbi t
TE28F800C3TD70
TE28F800C3BD70
TE28F800C3TA90
TE28F800C3BA90
TE28F800C3TA110
TE28F800C3BA110
JS28F800C3BD70
JS28F800C3TD70
RC28F800C3TD70
RC28F800C3BD70
RC28F800C3TA90
RC28F800C3BA90
RC28F800C3TA110
RC28F800C3BA110
PC28F800C3BD70
PC28F800C3TD70
Note: The second line of the 48 - ball µBGA pack age top side mark specifies assembly codes. For samples
only, the f ir st char acter signif ies eit her “E” for en gineer ing samples or “S ” for sili con da isy chain
sam ples. A ll oth er assembly codes w it hout an “E ” or “S” as the fi rs t charact er ar e pr oduc t ion units.
