ky M29F800AT M29F800AB 8 Mbit (1Mb x8 or 512Kb x16, Boot Block) Single Supply Flash Memory SINGLE 5V+10% SUPPLY VOLTAGE for PROGRAM, ERASE and READ OPERATIONS ACCESS TIME: 70ns m PROGRAMMING TIME 8us per Byte/Word typical 19 MEMORY BLOCKS 1 Boot Block (Top or Bottom Location) 2 Parameter and 16 Main Blocks PROGRAM/ERASE CONTROLLER Embedded Byte/Word Program algorithm Embedded Multi-Block/Chip Erase algorithm Status Register Polling and Toggle Bits Ready/Busy Output Pin ERASE SUSPEND and RESUME MODES Read and Program another Block during Erase Suspend TEMPORARY BLOCK UNPROTECTION MODE LOW POWER CONSUMPTION Standby and Automatic Standby 100,000 PROGRAM/ERASE CYCLES per BLOCK 20 YEARS DATA RETENTION Defectivity below 1 ppm/year ELECTRONIC SIGNATURE Manufacturer Code: 0020h M29F800AT Device Code: OOECh M29F800AB Device Code: 0058h October 1999 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PRELIMINARY DATA TSOP 48 (N) 12 x 20mm Figure 1. Logic Diagram Voc 19 15 A0-A18 BD KB> da0-pa14 wo i DOQ15A-1 - M29F800AT ___ E meers00an P BYTE qGd O RB ee Vss Al02198B 1/21M29F800AT, M29F800AB Figure 2A. TSOP Connections Figure 2B. SO Connections ADT \ 48 = A16 Ali4ce = BYTE A13 rm Vss A129 DQ15A-1 Aco DQ7 A10co Da14 AIC r DQ6 A8 co = DAI3 NC co 9 DQ5 NC cg DQi2 woo Da4 RP 412 m29Fs00AT 37 Vcc NC coaji3 M29F800AB 36 f5DQ11 NC oo rj DQ3 RB ES DQi0 Alig co 7 DQ2 A117 7 DQ9 AT CS Dai A6 Co r DQ8 A5 cS Dao A4c9 1G A3 C3 rmaVss A?cg HE At m= 724 25 F=Ao \ Al02199 RB cSt) 44 [4 RP A182 4359 W Ai7e393 42 A8 A7tU4 41 Co Ag A6ro5 40 Ai0 A5rcoa6 39] Alt A4ccq7 38 A12 A3c38 37 | A13 A2cg9 365 A14 Aico 10 355 A15 AO T7711 M29F800AT 34 FQ A16 E [7] 12 M29F800AB 33 [23 BYTE Vss 4 13 32 Vss Goeg14 31 [5 DQ15A-1 DQO m5 15 30 [=] DQ7 DQ8 tH 16 295 Da14 DQi cS 17 28 [=] DQ6 DQ9 es 18 273 DQi3 DQ2 e519 26 [= DQ5 DQ10 Gj 20 25 (= DQ12 DQ3 5 21 24 [= DQ4 DQ11 |] 22 233F3Vcc Al02101B Table 1. Signal Names A0-A18 Address Inputs DQ0-DQ7 Data Inputs/Outputs DQ8-DQ1 4 Data Inputs/Outputs DQ15A-1 Data Input/Output or Address Input E Chip Enable G Output Enable Ww Write Enable RP Reset/Block Temporary Unprotect RB Ready/Busy Output BYTE Byte/Word Organization Select Vcc Supply Voltage Vss Ground NG Not Connected Internally 2/21 SUMMARY DESCRIPTION The M29F800A is an 8 Mbit (1Mb x8 or 512Kb x16) non-volatile memory that can be read, erased and reprogrammed. These operations can be per- formed using a single 5V supply. On power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or EPROM. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. Each block can be protected independently to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are writ- ten to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. kyM29F800AT, M29F800AB Table 2. Absolute Maximum Ratings ) Symbol Parameter Value Unit Ambient Operating Temperature (Temperature Range Option 1) 0 to 70 C Ta Ambient Operating Temperature (Temperature Range Option 6) 40 to 85 C Ambient Operating Temperature (Temperature Range Option 3) 40 to 125 C TBIAS Temperature Under Bias 50 to 125 C TstG Storage Temperature 65 to 150 C Vio 2) Input or Output Voltage -0.6 to6 V Voc Supply Voltage -0.6 to 6 V Vip Identification Voltage -0.6 to 13.5 Vv Note: 1. Except for the rating "Operating Temperature Range, stresses above those listed in the Table "Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi- tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual- ity documents. 2. Minimum Voltage may undershoot to 2V during transition and for less than 20ns during transitions. The blocks in the memory are asymmetrically ar- ranged, see Tables 3A and 3B, Block Addresses. The first or last 64 Kbytes have been divided into four additional blocks. The 16 Kbyte Boot Block can be used for small initialization code to start the microprocessor, the two 8 Kbyte Parameter Blocks can be used for parameter storage and the remaining 32K is a small Main Block where the ap- plication may be stored. Chip Enable, Output Enable and Write Enable sig- nals control the bus operation of the memory. They allow simple connection to most micropro- cessors, Often without additional logic. The memory is offered in TSOP48 (12 x 20mm) and SO44 packages. Access times of 70ns and 90ns are available. The memory is supplied with all the bits erased (set to 1). SIGNAL DESCRIPTIONS See Figure 1, Logic Diagram, and Table 1, Signal Names, for a brief overview of the signals connect- ed to this device. Address Inputs (A0-A18). The Address Inputs select the cells in the memory array to access dur- ing Bus Read operations. During Bus Write opera- tions they control the commands sent to the Command Interface of the internal state machine. 4 Data Inputs/Outputs (DQ0-DQ7). The Data In- puts/Outputs output the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the internal state machine. Data Inputs/Outputs (DQ8-DQ14). The Data In- puts/Outputs output the data stored at the selected address during a Bus Read operation when BYTE is High, Viy. When BYTE is Low, Vj_, these pins are not used and are high impedance. During Bus Write operations the Command Register does not use these bits. When reading the Status Register these bits should be ignored. Data Input/Output or Address Input (DQ15A-1). When BYTE is High, Vip, this pin behaves as a Data _ Input/Output pin (as DQ8-DQ14). When BYTE is Low, Vi, this pin behaves as an address pin; DQ15A1 Low will select the LSB of the Word on the other addresses, DQ15A-1 High will select the MSB. Throughout the text consider references to the Data Input/Output to include this pin when BYTE is High and references to the Address In- puts to include this pin when BYTE is Low except when stated explicitly otherwise. 3/21M29F800AT, M29F800AB Table 3A. M29F800AT Block Addresses Table 3B. M29F800AB Block Addresses Size Address Range Address Range Size Address Range Address Range (Kbytes) (x8) (x16) (Kbytes) (x8) (x16) 16 FCOOO0h-FFFFFh 7E000h-7FFFFh 64 FOOOOh-FFFFFh 78000h-7FFFFh 8 FA000h-FBFFFh 7D000h-7DFFFh 64 E0000h-EFFFFh 70000h-77FFFh 8 F8000h-F9FFFh 7C000h-7CFFFh 64 DOO000h-DFFFFh 68000h-6FFFFh 32 FOOOO0h-F7FFFh 78000h-7BFFFh 64 C0000h-CFFFFh 60000h-67FFFh 64 E0000h-EFFFFh 70000h-77FFFh 64 BOO00h-BFFFFh 58000h-5FFFFh 64 DO000h-DFFFFh 68000h-6FFFFh 64 A0000h-AFFFFh 50000h-57FFFh 64 C0000h-CFFFFh 60000h-67FFFh 64 90000h-9FFFFh 48000h-4FFFFh 64 BooO00h-BFFFFh 58000h-5FFFFh 64 80000h-8FFFFh 40000h-47FFFh 64 A0000h-AFFFFh 50000h-57FFFh 64 70000h-7FFFFh 38000h-3FFFFh 64 90000h-9FFFFh 48000h-4FFFFh 64 60000h-6FFFFh 30000h-37FFFh 64 80000h-8FFFFh 40000h-47FFFh 64 50000h-5FFFFh 28000h-2FFFFh 64 70000h-7FFFFh 38000h-3FFFFh 64 40000h-4FFFFh 20000h-27FFFh 64 60000h-6FFFFh 30000h-37FFFh 64 30000h-3FFFFh 18000h-1FFFFh 64 50000h-5FFFFh 28000h-2FFFFh 64 20000h-2FFFFh 10000h-17FFFh 64 40000h-4FFFFh 20000h-27FFFh 64 10000h-1FFFFh 08000h-OFFFFh 64 30000h-3FFFFh 18000h-1FFFFh 32 08000h-OFFFFh 04000h-07FFFh 64 20000h-2FFFFh 10000h-17FFFh 8 06000h-07FFFh 03000h-03FFFh 64 10000h-1FFFFh 08000h-OFFFFh 8 04000h-O05FFFh 02000h-02FFFh 64 00000h-OFFFFh 00000h-07FFFh 16 00000h-03FFFh 00000h-01FFFh Chip Enable (E). The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write op- erations to be performed. When Chip Enable is High, Vp, all other pins are ignored. Output Enable (G). The Output Enable, G, con- trols the Bus Read operation of the memory. Write Enable (W). The Write Enable, W, controls the Bus Write operation of the memorys Com- mand Interface. Reset/Block Temporary Unprotect (RP). The Re- set/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to tem- porarily unprotect all blocks that have been pro- tected. A Hardware Reset is achieved by holding Reset/ Block Temporary Unprotect Low, Vj, for at least tp_px. After Reset/Block Temporary Unprotect goes High, Vi, the memory will be ready for Bus Read and Bus Write operations after tpye_ or tRHEL, whichever occurs last. See the Ready/Busy Output section, Table 14 and Figure 10, Reset/ Temporary Unprotect AC Characteristics for more details. Holding RP at Vip will temporarily unprotect the protected blocks in the memory. Program and Erase operations on all blocks will be possible. 4/21 The transition from Viy to Vip must be slower than tPHPHH.- Ready/Busy Output (RB). The Ready/Busy pin is an open-drain output that can be used to identify when the memory array can be read. Ready/Busy is high-impedarce during Read mode, Auto Select mode and Erase Suspend mode. After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy be- comes high-impedance. See Table 14 and Figure 10, Reset/Temporary Unprotect AC Characteris- tics. During Program or Erase operations Ready/Busy is Low, VoL. Ready/Busy will remain Low during Read/Reset commands or Hardware Resets until the memory is ready to enter Read mode. The use of an open-drain output allows the Ready/ Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy. Byte/Word Organization Select (BYTE). The Byte/ Word Organization Select pin is used to switch be- tween the 8-bit and 16-bit Bus modes of the mem- ory. When Byte/Word Organization Select is Low, ViL; the memory is in 8-bit mode, when it is High, Vio; the memory is in 16-bit mode. kyM29F800AT, M29F800AB Table 4A. Bus Operations, BYTE = Vit _ _ _ Data Inputs/Outpu ts Operation E G Ww DOTeA ip ve Q15A-1, AO- DQ14-DQ8 DQ7-DQ0 Bus Read VIL VIL ViIH Cell Address Hi-Z Data Output Bus Write Vit Vin VIL Command Address Hi-Z Data Input Output Disable Xx Vin Vin xX Hi-Z Hi-Z Standby Vin xX xX xX Hi-Z Hi-Z Read Manufacturer AO = ViL, Al = ViL, AQ = Vip, . Code Vit Vit Vi Others Vi_ or Vin Hi-Z 20h . AO = Vin, Al = Vi_, AO = Vip, . ECh (M29F800AT) Vv - Read Device Code IL Vit |} YH | others Vitor Vi Hz 58h (M29F800AB) Note: X = Vi_ or Viv. Table 4B. Bus Operations, BYTE = Vin : = = wz Address Inputs Data Inputs/Outpu ts Operation E G Ww A0-A18 DQ15A-1, DQ14-DaQ0 Bus Read VIL VIL ViH Cell Address Data Output Bus Write Vit Vin VIL Command Address Data Input Output Disable Xx ViH Vin |X Hi-Z Standby VIH X X X Hi-Z Read Manufacturer AO = Vi, Al = Vi, A9 = Vip, Code Vit VIL VIH Others Vj or Vin 0020h . AO = Vin, Al = ViL, A9 = Vip, OOECh (M29F800AT) Read Device Code Vit Vit Vi | Others Vir or Vin 0058h (M29F800AB) Note: X = Vi_ or Vip. Vcc Supply Voltage. The Vcc Supply Voltage supplies the power for all operations (Read, Pro- gram, Erase etc.). The Command Interface is disabled when the Vcc Supply Voltage is less than the Lockout Voltage, Viko. This prevents Bus Write operations from ac- cidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memo- ry contents being altered will be invalid. A 0.1pF capacitor should be connected between the Vcc Supply Voltage pin and the Vss Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations, Icca. Vss Ground. The Vss Groundis the reference for all voltage measurements. ky BUS OPERATIONS There are five standard bus operations that control the device. These are Bus Read, Bus Write, Out- put Disable, Standby and Automatic Standby. See Tables 4A and 4B, Bus Operations, for a summa- ry. Typically glitches of less than 5ns on Chip En- able or Write Enable are ignored by the memory and do not affect bus operations. Bus Read. Bus Read operations read from the memory cells, or specific registers in the Com- mand Interface. A valid Bus Read operation in- volves setting the desired address on the Address Inputs, applying a Low signal, Vi_, to Chip Enable and Output Enable and keeping Write Enable High, Vi. The Data Inputs/Outputs will output the value, see Figure 7, Read Mode AC Waveforms, and Table 11, Read AC Characteristics, for details of when the output becomes valid. Bus Write. Bus Write operations write to the Command Interface. A valid Bus Write operation 5/21M29F800AT, M29F800AB begins by setting the desired address on the Ad- dress Inputs. The Address Inputs are latched by the Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the Com- mand Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output En- able must remain High, Vj, during the whole Bus Write operation. See Figures 8 and 9, Write AC Waveforms, and Tables 12 and 13, Write AC Characteristics, for details of the timing require- ments. Output Disable. The Data Inputs/Outputs are in the high impedance state when Output Enable is High, Vp. Standby. When Chip Enable is High, Vjy, the Data Inputs/Outputs pins are placed in the high- impedance state and the Supply Current is re- duced to the Standby level. When Chip Enable is at Vj the Supply Current is reduced to the TTL Standby Supply Current, Iccoe. To further reduce the Supply Current to the CMOS Standby Supply Currert, Icc3, Chip Enable should be held within Vec + 0.2V. For Standby current levels see Table 10, DC Characteristics. During program or erase operations the memory will continue to use the Program/Erase Supply Current, Icca, for Program or Erase operations un- til the operation completes. Automatic Standby. If CMOS levels (Vcc + 0.2V) are used to drive the bus and the bus is inactive for 150ns or more the memory enters Automatic Standby where the internal Supply Current is re- duced to the CMOS Standby Supply Current, Icc3. The Data Inputs/Outputs will still output data if a Bus Read operation is in progress. Special Bus Operations Additional bus operations can be performed to read the Electronic Signature and also to apply and remove Block Protection. These bus opera- tions are intended for use by programming equip- ment and are not usually used in applications. They require Vip to be applied to some pins. Electronic Signature. The memory has_ two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can be read by applying the signals listed in Tables 4A and 4B, Bus Operations. Block Protection and Blocks Unprotection. Each block can be separately protected against acci- dental Program or Erase. Protected blocks can be unprotected to allow data to be changed. There are two methods available for protecting and unprotecting the blocks, one for use on pro- gramming equipment and the other for in-system use. For further information refer to Application Note AN1122, Applying Protection and Unprotec- tion to M29 Series Flash. 6/21 COMMAND INTERFACE All Bus Write operations to the memory are inter- preted by the Command Interface. Commands consist of one or more sequential Bus Write oper- ations. Failure to observe a valid sequence of Bus Write operations will result in the memory return- ing to Read mode. The long command sequences are imposed to maximize data security. The address used for the commands changes de- pending on whether the memory is in 16-bit or 8- bit mode. See either Table 5A, or 5B, depending on the configuration that is being used, for a sum- mary of the commands. Read/Reset Command. The Read/Reset com- mand returns the memory to its Read mode where it behaves like a ROM or EPROM. It also resets the errors in the Status Register. Either one or three Bus Write operations can be used to issue the Read/Reset command. If the Read/Reset command is issued during a Block Erase operation or following a Programming or Erase errorthen the memory will take up to 1 Ous to abort. During the abort period no valid data can be read from the memory. Issuing a Read/Reset command during a Block Erase operation will leave invalid data in the memory. Auto Select Command. The Auto Select com- mand is used to read the Manufacturer Code, the Device Code and the Block Protection Status. Three consecutive Bus Write operations are re- quired to issue the Auto Select command. Once the Auto Select command is issued the memory remains in Auto Select mode until another com- mand is issued. From the Auto Select mode the Manufacturer Code can be read using a Bus Read operation with AO = Vi_ andA1 = Vj_. The other address bits may be set to either Vi_ or Vi. The Manufacturer Code for STMicroelectronics is 0020h. The Device Code can be read using a Bus Read operation with AO = Viy and Ai = Vj_. The other address bits may be set to either Vj_ or Vi. The Device Code for the M29F800AT is OOECh and for the M29F800AB is 0058h. The Block Protection Status of each block can be read using a Bus Read operation with AO = VL, Al = Vin, and A12-A18 specifying the address of the block. The other address bits may be set to ei- ther V\_ or Vip. If the addressed block is protected then 01h is output on Data Inputs/Outputs DQO- DQ7, otherwise 00h is output. Program Command. The Program command can be used to program a value to one address in the memory array at a time. The command re- quires four Bus Write operations, the final write op- eration latches the address and data in the internal state machine and starts the Program/Erase Con- troller. kyM29F800AT, M29F800AB Table 5A. Commands, 16-bit mode, BYTE = Vin c Bus Write Operations Command 2 ist 2nd 3rd 4th 5th 6th 4 Addr | Data | Addr | Data | Addr | Data | Addr | Data | Addr | Data | Addr | Data 1 X FO Read/Reset 3 | 555 AA | 2AA 55 x FO Auto Select 3 | 555 | AA | 2AA | 55 555 90 Program 4 | 555 | AA | 2AA | 55 555 AO PA PD Chip Erase 6 | 555 AA | 2AA 55 555 80 555 AA | 2AA 55 555 10 Block Erase 6+ | 555 AA | 2AA 55 555 80 555 AA | 2AA 55 BA 30 Erase Suspend 1 x BO Erase Resume 1 X 30 Table 5B. Commands, 8-bit mode, BYTE = Vit c Bus Write Operations Command 2 ist 2nd 3rd 4th 5th 6th 4 Addr | Data | Addr | Data | Addr | Data | Addr | Data | Addr | Data | Addr | Data 1 X FO Read/Reset 3 |] AAA] AA | 555 | 55 X FO Auto Select 3 | AAA | AA | 555 55 | AAA | 90 Program 4 | AAA | AA | 555 55 | AAA | AO PA PD Chip Erase 6 | AAA | AA | 555 | 55 | AAA] 80 | AAA | AA | 555 | 55 | AAA] 10 Block Erase 6+] AAA | AA | 555 | 55 | AAA] 80 | AAA] AA | 555 | 55 BA 30 Erase Suspend 1 x BO Erase Resume 1 X 30 Note: X Dont Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal. The Command Interface only uses A-1, AO-A10 and_DQO-DQ7 to verify the commands; A11-A18, DQ8-DQ14 and DQ15 are Dont Care. DQ15A-1 is A-1 when BYTE is V\_ or DQ15 when BYTE is Vip. Read/Reset. After a Read/Reset command, read the memory as normal until another command is issued. Auto Select. After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status. Program, Chip Erase, Block Erase. After these commands read the Status Register until the Program/Erase Controller completes and the memory returns to Read Mode. Add additional Blocks during Block Erase Command with additional Bus Write Operations until the Timeout Bit is set. Erase Suspend. After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto Select and Program commands on non-erasing blocks as normal. Erase Resume. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the Program/ Erase Controller completes and the memory returns to Read Mode. If the address falls in a protected block then the Program command is ignored, the data remains unchanged. The Status Register is never read and no error condition is given. During the program operation the memory will ig- nore all commands. It is not possible to issue any command to abort or pause the operation. Typical program times are given in Table 6. Bus Read op- erations during the program operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. ky After the program operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Regis- ter. A Read/Reset command must be issued to re- set the error condition and return to Read mode. Note that the Program command cannot change a bit set at 0 back to 1 and attempting to do so will cause an error. One of the Erase Commands must be used to set all the bits in a block or in the whole memory from 0 to 1. 7/21M29F800AT, M29F800AB Table 6. Program, Erase Times and Program, Erase Endurance Cycles (Ta = 0 to 70C, 40 to 85C or 40 to 125C) Parameter Min Typ 4 ook WIE Cycies (1) Max Unit Chip Erase (All bits in the memory set to 0) 3 3 sec Chip Erase 8 8 30 sec Block Erase (64 Kbytes) 0.6 0.6 4 sec Program (Byte or Word) 8 8 150 us Chip Program (Byte by Byte) 9 9 35 sec Chip Program (Word by Word) 45 45 18 sec Program/Erase Cycles (per Block) 100,000 cycles Note: 1. Ta = 25C, Voc = 5V. Chip Erase Command. The Chip Erase com- mand can be used to erase the entire chip. Six Bus Write operations are required to issue the Chip Erase Command and start the Program/Erase Controller. If any blocks are protected then these are ignored and all the other blocks are erased. If all of the blocks are protected the Chip Erase operation ap- pears to start but will terminate within about 100us, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the erase operation the memory will ignore all commands. It is not possible to issue any com- mand to abort the operation. Typical chip erase times are given in Table 6. All Bus Read opera- tions during the Chip Erase operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the Chip Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Regis- ter. A Read/Reset command must be issued to re- set the error condition and return to Read Mode. The Chip Erase Command sets all of the bits in un- protected blocks of the memory to 1. All previous data is lost. Block Erase Command. The Block Erase com- mand can be used to erase a list of one or more blocks. Six Bus Write operations are required to select the first block in the list. Each additional block in the list can be selected by repeating the sixth Bus Write operation using the address of the additional block. The Block Erase operation starts the Program/Erase Controller about 50us after the last Bus Write operation Once the Program/Erase 8/21 Controller starts it is not possible to select any more blocks. Each additional block must therefore be selected within 50us of the last block. The 50us timer restarts when an additional block is selected. The Status Register can be read after the sixth Bus Write operation. See the Status Register for details on how to identify if the Program/Erase Controller has started the Block Erase operation. If any selected blocks are protected then these are ignored and all the other selected blocks are erased. If all of the selected blocks are protected the Block Erase operation appears to start but will terminate within about 100us, leaving the data un- changed. No error condition is given when protect- ed blocks are ignored. During the Block Erase operation the memory will ignore all commands except the Erase Suspend and Read/Reset commands. Typical block erase times are given in Table 6. All Bus Read opera- tions during the Block Erase operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the Block Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Regis- ter. A Read/Reset command must be issued to re- set the error condition and return to Read mode. The Block Erase Command sets all of the bits in the unprotected selected blocks to 1. All previous data in the selected blocks is lost. Erase Suspend Command. The Erase Suspend Command may be used to temporarily suspend a Block Erase operation and return the memory to Read mode. The command requires one Bus Write operation. kyM29F800AT, M29F800AB Table 7. Status Register Bits Operation Address DQ7 DQG DQ5 DQ3 DQ2 RB Program Any Address DQ7 Toggle 0 - - 0 Program During Erase Day _ _ Suspend Any Address DQ7 Toggle 0 0 Program Error Any Address DQ7 Toggle 1 - - 0 Chip Erase Any Address 0 Toggle 0 1 Toggle 0 Block Erase before Erasing Block 0 Toggle 0 0 Toggle 0 timeout Non-Erasing Block 0 Toggle 0 0 No Toggle 0 Erasing Block 0 Toggle 0 1 Toggle 0 Block Erase Non-Erasing Block 0 Toggle 0 1 No Toggle 0 Erasing Block 1 No Toggle 0 1 Toggle 1 Erase Suspend Non-Erasing Block Data read as normal 1 Good Block Address 0 Toggle 1 1 No Toggle 0 Erase Error Faulty Block Address 0 Toggle 1 1 Toggle 0 Note: Unspecified data bits should be ignored. The Program/Erase Controller will suspend within 15us of the Erase Suspend Command being is- sued. Once the Program/Erase Controller has stopped the memory will be set to Read mode and the Erase will be suspended. If the Erase Suspend command is issued during the period when the memory is waiting for an additional block (before the Program/Erase Controller starts) then the Erase is suspended immediately and will start im- mediately when the Erase Resume Command is issued. It will not be possible to select any further blocks for erasure after the Erase Resume. During Erase Suspend it is possible to Read and Program cells in blocks that are not being erased; both Read and Program operations behave as normal on these blocks. Reading from blocks that are being erased will output the Status Register. It is also possible to enter the Auto Select mode: the memory will behave as in the Auto Select mode on all blocks until a Read/Reset command returns the memory to Erase Suspend mode. Erase Resume Command. The Erase Resume command must be used to restart the Program/ Erase Controller from Erase Suspend. An erase can be suspended and resumed more than once. STATUS REGISTER Bus Read operations from any address always read the Status Register during Program and Erase operations. It is also read during Erase Sus- ky pend when an address within a block being erased is accessed. The bits in the Status Register are summarized in Table 7, Status Register Bits. Data Polling Bit (DQ7). The Data Polling Bit can be used to identify whether the Program/Erase Controller has successfully completed its opera- tion or if it has responded to an Erase Suspend. The Data Polling Bit is output on DQ7 when the Status Register is read. During Program operations the Data Polling Bit outputs the complement of the bit being pro- grammed to DQ7. After successful completion of the Program operation the memory returns to Read mode and Bus Read operations from the ad- dress just programmed output DQ7, not its com- plement. During Erase operations the Data Polling Bit out- puts 0, the complement of the erased state of DQ7. After successful completion of the Erase op- eration the memory returns to Read Mode. In Erase Suspend mode the Data Polling Bit will output a 1 during a Bus Read operation within a block being erased. The Data Polling Bit will change from a0 to a1 when the Program/Erase Controller has suspended the Erase operation. Figure 3, Data Polling Flowchart, gives an exam- ple of how to use the Data Polling Bit. A Valid Ad- dress is the address being programmed or an address within the block being erased. 9/21M29F800AT, M29F800AB Figure 3. Data Polling Flowchart Figure 4. Data Toggle Flowchart START READ DQ5 & DQ7 at VALID ADDRESS {| FAL | | Pass | Al01369 START READ DQ5 & DQ6 Das TOGGLE YES : YES READ DQ6 Das TOGGLE YES {| FAL | | Pass {| Al01370 Toggle Bit (DQ6). The Toggle Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has re- sponded to an Erase Suspend. The Toggle Bit is output on DQ6 when the Status Register is read. During Program and Erase operations the Toggle Bit changes from 0 to 1 to0, etc., with Succes- sive Bus Read operations at any address. After successful completion of the operation the memo- ry returns to Read mode. During Erase Suspend mode the Toggle Bit will output when addressing a cell within a block being erased. The Toggle Bit will stop toggling when the Program/Erase Controller has suspended the Erase operation. Figure 4, Data Toggle Flowchart, gives an exam- ple of how to use the Data Toggle Bit. Error Bit (DQ5). The Error Bit can be used to identify errors detected by the Program/Erase Controller. The Error Bit is set to 1 when a Pro- 10/21 gram, Block Erase or Chip Erase operation fails to write the correct data to the memory. If the Error Bit is set a Read/Reset command must be issued before other commands are issued. The Error bit is output on DQ5 when the Status Register is read. Note that the Program command cannot change a bit set at 0 back to 1 and attempting to do so will cause an error. One of the Erase Commands must be used to set all the bits in a block or in the whole memory from 0 to 1. Erase Timer Bit (DQ3). The Erase Timer Bit can be used to identify the start of Program/Erase Controller operation during a Block Erase com- mand. Once the Program/Erase Controller starts erasing the Erase Timer Bit is set to 1. Before the Program/Erase Controller starts the Erase Timer Bit is set to 0 and additional blocks to be erased may be written to the Command Interface. The Erase Timer Bit is output on DQ3 when the Status Register is read. 4]Table 8. AC Measurement Conditions M29F800AT, M29F800AB M29F800A Parameter 70 90 AC Test Conditions High Speed Standard Load Capacitance (C_) 30pF 100pF Input Rise and Fall Times <10ns <10ns Input Pulse Voltages 0 to 3V 0.45 to 2.4V Input and Output Timing Ref. Voltages 1.5V 0.8V and 2.0V Figure 5. AC Testing Input Output Waveform Figure 6. AC Testing Load Circuit 1.3V High Speed 3V 1N914 ov 3.3kQ DEVICE Standard UNDER OUT TEST 2.4 T on = 30pF or 100pF 0.45V : Al01275B C__ includes JIG capacitance 103027 Table 9. Capacitance (Ta = 25C, f = 1 MHz) Symbol Parameter Test Condition Min Max Unit CIN Input Capacitance Vin = OV 6 pF CouT Output Capacitance VouT = 0V 12 pF Note: Sampled only, not 100% tested. 4] 11/21M29F800AT, M29F800AB Table 10. DC Characteristics (Ta = 0 to 70C, 40 to 85C or 40 to 125C) Symbol Parameter Test Condition Min Typ. @ Max Unit IL Input Leakage Current OV < Vin $ Voc + HA ILo Output Leakage Current OV < VouT < Vcc +1 HA lect Supply Current (Read) E=Vi, G= Vin, f= 6MHz 10 20 mA Ioc2 Supply Current (Standby) TTL E=Vin 1 mA lcc3__| Supply Current (Standby) CMOS FP oy 35 150 WA loca ) | Supply Current (Program/Erase) Cor Erase 20 mA VIL Input Low Voltage 0.5 0.8 Vv Vin Input High Voltage 2 Vec+05] V VoL Output Low Voltage lo. = 5.8mMA 0.45 Vv Output High Voltage TTL loH = -2.5mA 2.4 Vv You Output High Voltage CMOS loH = 100nA Voc 0.4 V Vip Identification Voltage 11.5 12.5 V lip Identification Current AQ =Vip 100 HA ViKo"") Voluge Lockout Supply 30 42 V Note: 1. Sampled only, not 100% tested. 2. Ta = 25C, Voc =5V. Alternative Toggle Bit (DQ2). The Alternative blocks being erased. Bus Read operations to ad- Toggle Bit can be used to monitor the Program/ Erase controller during Erase operations. The Al- ternative Toggle Bit is output on DQ2 when the Status Register is read. During Chip Erase and Block Erase operations the Toggle Bit changes from 0 to 1 to 0, etc., with successive Bus Read operations from addresses within the blocks being erased. Once the operation completes the memory returns to Read mode. During Erase Suspend the Alternative Toggle Bit changes from 0 to 1 to 0, etc. with successive Bus Read operations from addresses within the 12/21 dresses within blocks not being erased will output the memory cell data as if in Read mode. After an Erase operation that causes the Error Bit to be set the Alternative Toggle Bit can be used to identify which block or blocks have caused the er- ror. The Alternative Toggle Bit changes from 0 to 1 to 0, etc. with successive Bus Read Opera- tions from addresses within blocks that have not erased correctly. The Alternative Toggle Bit does not change if the addressed block has erased cor- rectly. 4]M29F800AT, M29F800AB Table 11. Read AC Characteristics (TA = Oto 70C, 40 to 85C or 40 to 125C) M29F800A Symbol Alt Parameter Test Condition Unit 70 90 . . E=Vi, . tavav tre Address Valid to Next Address Valid G=Vit Min 70 90 ns , E=Vu. tavav tacc Address Valid to Output Valid G=ViL Max 70 90 ns teLax (? tLz Chip Enable Low to Output Transition G=ViL Min 0 0 ns tELaV tcE Chip Enable Low to Output Valid G= VIL Max 70 90 ns tatax toLz | Output Enable Low to Output Transition E=Vi Min 0 0 ns tGLav toE Output Enable Low to Output Valid E= Vit Max 30 35 ns tEHQz ? tuz Chip Enable High to Output Hi-Z GeVit Max 20 20 ns teHaz ? tpF | Output Enable High to Output Hi-Z E=Vit Max 20 20 ns tEHQX . Chip Enable, Output Enable or . taHax toH Address Transition to Output Transition Min 0 0 ns tAXQX ELBL 'ELFL | Chip Enable to BYTE Low or High Max] 5 5 ns tELBH tELFH tBLaz tFLqz_ | BYTE Low to Output Hi-Z Max 20 20 ns tBHaV teHav | BYTE High to Output Valid Max 30 40 ns Note: 1. Sampled only, not 100% tested. Figure 7. Read Mode AC Waveforms < tAVAV | AO-A18/ ne x VALID x le tAVQV le tAXQX _ FT _ E , i <4 tELQV > mr tEHOX tELQX + Pt tEHQZ _ \ f G . ij 1tGLQX tGHQX - iGLQV > tGHQZ -1t > DQO-DQ7/ Y } DQ8-DQ15 a tBHQV BVTE \ BYTE j , tELBLAELBH > tBLQZ 1 Aloz981 iy 13/21M29F800AT, M29F800AB Table 12. Write AC Characteristics, Write Enable Controlled (Ta = 0 to 70 C, 40 to 85 C or 40 to 125 C) M29F800A Symbol Alt Parameter Unit 70 90 TAVAV two Address Valid to Next Address Valid Min 70 90 ns tELWL tcs Chip Enable Low to Write Enable Low Min 0 0 ns twLWH twp Write Enable Low to Write Enable High Min 45 45 ns tbVWH tps Input Valid to Write Enable High Min 30 45 ns twHDx tbH Write Enable High to Input Transition Min 0 0 ns tWHEH tcH Write Enable High to Chip Enable High Min 0 0 ns tWHWL twPH Write Enable High to Write Enable Low Min 20 20 ns TAVWL tas Address Valid to Write Enable Low Min 0 0 ns tWLax taH Write Enable Low to Address Transition Min 45 45 ns tGHWL Output Enable High to Write Enable Low Min 0 0 ns tWHGL toEH Write Enable High to Output Enable Low Min 0 0 ns twoer tpusy |Program/Erase Valid to RB Low Max 30 35 ns tVCHEL tvcs Voc High to Chip Enable Low Min 50 50 ps Note: 1. Sampled only, not 100% tested. Figure 8. Write AC Waveforms, Write Enable Controlled jt tAVAV | AO-A18/ ne VALID tWLAX | tAVWL> h# tWHEH E \ tELWL ht tWHGL 6 4 tGHWL. .. tWLWH #| " _) @ itWHWL iDVWH tWHDX DQ0-DQ7/ DQ8-DQ15 VALID Voc | tVCHEL * RB tWHRL * Alo2183 14/21 4]M29F800AT, M29F800AB Table 13. Write AC Characteristics, Chip Enable Controlled (Ta = 0 to 70 C, 40 to 85 C or -40 to 125 C) M29F800A Symbol Alt Parameter Unit 70 90 tavav two Address Valid to Next Address Valid Min 70 90 ns tWLEL tws Write Enable Low to Chip Enable Low Min 0 0 ns tELEH tcp Chip Enable Low to Chip Enable High Min 45 45 ns tDVEH tps Input Valid to Chip Enable High Min 30 45 ns tEHDX tbH Chip Enable High to Input Transition Min 0 0 ns tEHWH tWH Chip Enable High to Write Enable High Min 0 0 ns tEHEL tcPH Chip Enable High to Chip Enable Low Min 20 20 ns tAVEL tas Address Valid to Chip Enable Low Min 0 0 ns tELAX taH Chip Enable Low to Address Transition Min 45 45 ns IGHEL Output Enable High Chip Enable Low Min 0 0 ns TEHGL toEH Chip Enable High to Output Enable Low Min 0 0 ns tenrr ? tpusy |Program/Erase Valid to RB Low Max 30 35 ns tvCHWL tvcs Voc High to Write Enable Low Min 50 50 ps Note: 1. Sampled only, not 100% tested. Figure 9. Write AC Waveforms, Chip Enable Controlled jt tAVAV > A0-A18/ nt VALID tELAX | tAVEL * t# tEHWH W \ ] tWLEL #_ tEHGL G | tGHEL rat tELEH * = / t#_ tEHEL tDVEH tEHDX DQ0-DQ7/ DQ8-DQ15 VALID Voc | tVCHWL RB tEHRL = Alo2184 YT 15/21M29F800AT, M29F800AB Table 14. Reset/Block Temporary Unprotect AC Characteristics (Ta = 0 to 70 C, 40 to 85 C or -40 to 125 C) M29F800A Symbol Alt Parameter Unit 70 90 te RP High to Write Enable Low, Chip Enable Low PHEL "RH Output Enable Low Min 60 60 ns tPHGL trowe = i (1) i RB High to Write Enable Low, Chip Enable Low, Min 0 0 ns RHEL , RB Output Enable Low trHat tpLPx tre | RP Pulse Width Min 500 500 ns teLyy | trEapy |RP Low to Read Mode Max 10 10 us teypay tvipR | RP Rise Time to Vip Min 500 500 ns Note: 1. Sampled only, not 100% tested. Figure 10. Reset/Block Temporary Unprotect AC Waveforms WEG \ ft iPHWL, tPHEL, tPHGL * RB , tf ee nooo tRHWL, tRHEL, tRHGL t *tPLPX * RP _ tPLYH } tPHPHH Al02931 16/21 4]M29F800AT, M29F800AB Table 15. Ordering Information Scheme Example: M29F800AB 70 N 1 = T Device Type M29 Operating Voltage F =Vcc =5V +10% Device Function 800A = 8Mbit (1 Mb x8 or 512Kb x16), Boot Block Array Matrix T = Top Boot B = Bottom Boot Speed 70 = 70ns 90 = 90 ns Package N = TSOP 48: 12 x 20 mm M = S044 Temperature Range 1=0to 70C 3 =40 to 125 C =40 to 85 C Option T = Tape & Reel Packing Note: The last two characters of the ordering code may be replaced by a letter code for preprogrammed parts, otherwise devices are shipped from the factory with the memory content erased (to FFFFh). For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de- vice, please contact the ST Sales Office nearest to you. 4] 17/21M29F800AT, M29F800AB Table 16. Revision History Date Revision Details July 1999 First Issue Removed 55ns speed option 09/21/99 loc1 Typ. specification added (Table 10) lcc3 Typ. specification added (Table 10) 10/04/99 lcc3 Test Condition change (Table 10) 18/21 4]M29F800AT, M29F800AB Table 17. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data mm inches Symbol Typ Min Max Typ Min Max A 1.20 0.047 Al 0.15 0.006 1.05 0.041 0.27 0.011 0.21 0.008 20.20 0.795 18.50 0.728 12.10 0.476 Figure 11. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline rf | j Es a A = 7 rT > i \ i i i __ 4 f f j s _ R - TSOP-a Al Drawing is not to scale. iy 19/21M29F800AT, M29F800AB Table 18. S044 - 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data mm inches Symbol Typ Min Max Typ Min Max 2.42 2.62 0.095 0.103 0.22 0.23 0.009 0.010 2.25 2.35 0.089 0.093 0.50 0.020 0.25 0.010 28.30 1.114 13.40 0.528 Figure 12. $044 - 44 lead Plastic Small Outline, 525 mils body width, Package Outline A C D 0 i ; ig ma | 1" / ; @ "4 A H H H I | Al a Ly SO-b Drawing is not to scale. 4] 20/21