LM5085EVAL/NOPB - NATIONAL SEMICONDUCTOR

LM5085 Evaluation Board National Semiconductor

Application Note 1878

Dennis Morgan

November 13, 2008

Introduction

The LM5085EVAL evaluation board provides the design en-

gineer with a fully functional buck regulator, employing the

LM5085 PFET switching controller which uses the constant

on-time (COT) operating principle. This evaluation board pro-

vides a 5V output over an input range of 5.5V to 55V. The

circuit delivers load currents to 4.5A, with current limit set at

≊7.6A. The board is populated with all components except

C5. Its use is described later in this document.

The board’s specification are:

•Input Voltage: 5.5V to 55V, 60V maximum

•Output Voltage: 5V

•Maximum load current: 4.5A for VIN >8V

•Minimum load current: 0A

•Current Limit Threshold: ≊7.6A

•Measured Efficiency: 97.2% (VIN = 5.5V, IOUT = 0.6Amps)

•Nominal Switching Frequency: 300 kHz

•Size: 3.1 in. x 1.5 in. x 0.78 in

30072001

FIGURE 1. Evaluation Board - Top Side

Theory of Operation

Refer to the evaluation board schematic in Figure 7. When

the circuit is in regulation, the on-time at the PGATE output

pin is determined by R4 and the voltage at VIN according to

the equation:

where R4 is in kohms. The on-time at the SW node (junction

of Q1, L1 and D1) is longer than the above calculated on-time

due to the difference of the turn-on and turn-off delay of Q1.

The data sheet for the Si7465 PFET indicates a typical turn-

on delay of 8 ns, and a typical turn-off delay of 65 ns, resulting

in an additional 57 ns at the SW node. The SW on-time of this

evaluation board ranges from ≊3479 ns at VIN = 5.5V, to

≊357 ns at VIN = 55V. The on-time varies inversely with VIN

to maintain a nearly constant switching frequency.

During the off-time, the load current is supplied by the inductor

and the output capacitor (C6, C7). When the output voltage

falls sufficiently that the voltage at FB is below the reference

voltage (1.25V), the regulation comparator initiates a new on-

time period. For stable, fixed frequency operation, a minimum

of 25 mV of ripple is required at the FB pin to switch the reg-

ulation comparator. The required ripple is generated by R7

and C10, and supplied to the FB pin via C9.

The current limit threshold is set by the sense resistor (R5),

and R3 at the ADJ pin, and is ≊7.6A on this board. A current

sink at the ADJ pin sets a constant voltage across R3. When

the voltage across R5 exceeds the voltage across R3 the

current limit comparator switches to shut off Q1, and the

LM5085 forces a longer-than-normal off-time. The long off-

time is a function of the input voltage (VIN) and the voltage at

the FB pin, and is necessary to allow the inductor current to

decrease at least as much, if not more, than the current in-

crease which occurred during the on-time.

The circuit may be shutdown at any time by grounding the

Enable test point (EN, TP1). Removing the ground connection

allows normal operation to resume.

LM5085 Evaluation Board AN-1878

Refer to the LM5085 data sheet for a detailed block diagram,

and a complete description of the various functional blocks.

Board Layout and Probing

The pictorial in Figure 1 shows the placement of the circuit

components. The following should be kept in mind when the

board is powered:

1) When operating at high input voltage and continuous con-

duction mode forced air flow is necessary to prevent over-

heating of the LM5085 controller.

2) When operating at high load current forced air flow may be

necessary to prevent overheating of Q1, D1, and L1. These

components may be hot to the touch.

3) Use CAUTION when probing the circuit at high input volt-

ages to prevent injury, as well as possible damage to the

circuit.

4) At maximum load current (4.5A), the wire size and length

used to connect the source voltage, and the load, becomes

important. Ensure there is not a significant drop in the wires

supplying the input current and the load current.

Board Connection/Start-up

The input connections are made to the J1 (+) and J2 (-) con-

nectors. The load is connected to the J3 (VOUT) and J4

(GND) terminals. Ensure the wires are adequately sized for

the intended load current. Before start-up a voltmeter should

be connected to the input terminals, and one to the output

terminals. The load current should be monitored with an am-

meter or a current probe. It is recommended that the input

voltage be increased gradually to 4.5V, at which time the out-

put voltage should be slightly less than 4.5V, depending on

the load current. The output is regulated at 5V when the input

voltage is increased above 5V. If the output voltage is correct,

then increase the input voltage as desired and proceed with

evaluating the circuit. DO NOT EXCEED 60V AT VIN. Ex-

ceeding 60V can result in damage to Q1 and/or D1.

Load Current Derating

Although the maximum load current for this evaluation board

is specified as 4.5A, the data sheet for the Si7465 PFET

specifies a maximum continuous current of 3.2A. Since the

input current, which is the average current though Q1, in-

creases as the input voltage is decreased, the load current

must be derated at low input voltage. Please refer to the graph

“Maximum Load Current Derating” below.

30072003

FIGURE 2. Maximum Load Current Derating

Operating at Low Voltage

When the input voltage is less than 5V the PFET (Q1) is on

continuously (100% duty cycle), and the output voltage is

equal to the input voltage, minus voltage drops across the

sense resistor, Q1 and the inductor. As the input voltage is

increased above 5V switching commences at the PGATE pin

and the SW node as the LM5085 regulates the output at 5V.

Since the LM5085 does not have a required minimum off-

time, the circuit transitions smoothly from 100% duty cycle to

a regulated output.

Current Limit

The LM5085 peak current limit detection operates by sensing

the voltage across either the RDS(ON) of Q1, or a sense resistor

(R5), during the on-time and comparing it to the voltage

across R3 at the ADJ pin. The current limit threshold is

reached when the sensed voltage exceeds the voltage across

R3. When current limit is reached Q1 is immediately switched

off. The current limit function is much more accurate and sta-

ble over temperature when a sense resistor is used. The RDS

(ON) of a MOSFET has a wide process variation and a large

temperature coefficient.

Current sensing is disabled for a blanking time of ≊100 ns at

the beginning of each on-time to prevent false triggering of

the current limit comparator due to leading edge current

spikes. After Q1 is turned off due to current limit detection, Q1

is held off for a longer-than-normal off-time. The extended off-

time is a function of the input voltage and the voltage at the

FB pin, as shown below in the graph “Current Limit Off-time

vs. VIN and VFB”. The current limit off-time can be calculated

from the following:

The longer-than-normal forced off-time allows the inductor

current to decrease to a low level before the next on-time. This

cycle-by-cycle monitoring, followed by a long forced off-time,

provides effective protection from output load faults over a

wide range of operating conditions.

30072005

FIGURE 3. Current Limit Off-time vs. VIN and VFB

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A) Sense resistor method – This evaluation board is sup-

plied configured for the sense resistor method of current limit

detection. Jumpers A-B are in place at both jumper locations

(JP1, JP2), which connects the ADJ pin resistor (R3) and the

ISEN pin across the sense resistor (R5). If the voltage across

R5 exceeds the voltage across R3 during the on-time, the

current limit comparator switches to turn off Q1. The voltage

across R3 is set by an internal 40 µA current sink at the ADJ

pin. The current at which the current limit comparator switches

is calculated from:

ICL = 40 µA x R3/R5 (1)

With R5 = 10 mΩ and R3 = 1.91 kΩ, the nominal current limit

threshold calculates to 7.64A. Since that is the peak of the

inductor current waveform, the load current is equal to that

peak value minus one half the ripple current amplitude. At Vin

= 5.5V, the ripple amplitude is 116 mAp-p, and the load cur-

rent at current limit is equal to 7.6 A. At Vin = 55V, the ripple

amplitude is 1190 mAp-p, and the load current at current limit

is equal to 7A.

Using the tolerances for the ADJ pin current and the current

limit comparator offset, the maximum current limit threshold

calculates to:

and the load current at current limit calculates to 10A at 5.5V,

and 9.5A at 55V. The minimum current limit thresholds cal-

culate to:

and the load current at current limit calculates to 5.15A at

5.5V, and 4.62A at 55V.

To change the current limit threshold the value for R5 should

be chosen to achieve 50 mV to 100 mV across it at current

limit, staying within the practical limitations of power dissipa-

tion and physical size of the resistor. A larger value for R5

reduces the effects of the current limit comparator offset, but

at the expense of higher power dissipation. After selecting the

value for R5, calculate the value for R3 by rearranging Equa-

tion 1 above. See the Applications Information section of the

LM5085 data sheet for a procedure to account for ripple cur-

rent amplitude and tolerances when selecting the resistor for

the ADJ pin.

B) Q1 RDS(ON) method – To configure the evaluation board

to use the RDS(ON) of Q1 for current limit detection, move the

jumpers at both JP1 and JP2 from the A-B position to the B-

C position. This change connects the ADJ pin resistor (R3)

and the ISEN pin across Q1. Since the sense resistance is

now the RDS(ON) of Q1, R3 must be changed. The data sheet

for the Si7465 PFET lists the typical RDS(ON) as 51 mΩ at

VGS = 10V, and 64 mΩ at VGS = 4.5V. Therefore, the RDS

(ON) is estimated to be nominally 57 mΩ at VGS = 7.7V. To

achieve the same nominal current limit threshold as above

(7.64A), using Equation 6 in the data sheet R3 calculates to:

The load current is equal to the current limit threshold minus

half the current ripple amplitude. R3 can be changed to set

other current limit detection thresholds.

Output Ripple Control

The LM5085 requires a minimum of 25 mVp-p ripple at the

FB pin, in phase with the switching waveform at the SW node,

for proper operation. On this evaluation board, the required

ripple is generated by R7, C9, and C10, allowing the ripple at

VOUT to be kept to a minimum, as described in option A below.

Alternatively, the required ripple at the FB pin can be supplied

from ripple generated at VOUT and passed through the feed-

back resistors, as described in options B and C below, using

one or two less external components.

A) Minimum Output Ripple: This evaluation board is sup-

plied configured for minimum ripple at VOUT by using compo-

nents R7, C9 and C10. The ripple voltage required by the FB

pin is generated by R7 and C10 since the SW node switches

from ≊-1V to VIN, and the right end of C10 is a virtual ground.

The values for R7 and C10 are chosen to generate a 25-40

mVp-p triangle waveform at their junction. That triangle wave

is then coupled to the FB pin through C9. The following pro-

cedure is used to calculate values for R7, C9 and C10:

1) Calculate the voltage VA:

VA = VOUT - (VSW x (1 - (VOUT/VIN(min))))

where VSW is the absolute value of the voltage at the SW node

during the off-time, typically 0.5V to 1V depending on the

diode, and VIN is the minimum input voltage. Using a typical

value of 0.65V for VSW, VA calculates to 4.94V. This is the

approximate DC voltage at the R7/C10 junction, and is used

in the next equation.

2) Calculate the R7xC10 product:

where tON is the maximum on-time (≊3479 ns), VIN is the min-

imum input voltage, and ΔV is the desired ripple amplitude at

the R7/C10 junction, 25 mVp-p for this example.

R7 and C10 are then chosen from standard value compo-

nents to satisfy the above product. On this evaluation board,

C10 is set at 3300 pF. R7 calculate to be 23.6 kΩ, and a stan-

dard value 23.2 kΩ resistor is used. C9 is chosen to be 0.01

µF, large compared to C10. The circuit as supplied on this

EVB is shown in Figure 4.

The output ripple, which ranges from ≊14 mVp-p at VIN = 5.5V

to ≊54 mVp-p at VIN = 55V, is determined primarily by the ESR

of the output capacitance (C6, C7), and the inductor’s ripple

current, which ranges from 116 mAp-p to 1190 mAp-p over

the input voltage range. See Figure 11.

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30072011

FIGURE 4. Minimum Ripple Using R7, C9, C10

B) Reduced Ripple Level Configuration: This configuration

generates more ripple at VOUT than the above configuration,

but uses one less capacitor. If some ripple is acceptable in

the application, this configuration is slightly more economical,

and simpler. R6 and C5 are used instead of R7, C9 and C10,

as shown in Figure 5.

Ripple is generated at VOUT as the inductor’s ripple current

flows through R6, and that ripple voltage is passed to the FB

pin via C5. The ripple at VOUT can be set as low as 25 mVp-

p since it is not attenuated by R1 and R2. The minimum value

for R6 is calculated from:

where IOR(min) is the minimum inductor’s ripple current, which

occurs at minimum input voltage, and is 116 mAp-p at 5.5V.

The minimum value for R6 calculates to 0.22 ohms. Using a

standard value 0.27Ω resistor for R6, the ripple at VOUT

ranges from 31 mVp-p to 321 mVp-p over the input voltage

range. See Figure 11.

The minimum value for C5 is determined from:

Where tON(max) is the maximum on-time, 3479 ns in this eval-

uation board. The minimum value for C5 calculates to 4113

pF.

30072012

FIGURE 5. Reduced Ripple Configuration

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C) Lowest Cost Configuration: This configuration is the

same as option B above, but with C5 removed. The ripple at

the FB pin is attenuated from that at VOUT by the feedback

resistors (R1, R2). Since ≥25 mVp-p are required at the FB

pin, R6 is chosen to generate ≥100 mV at VOUT. Since the

minimum ripple current in this circuit is 116 mAp-p the mini-

mum value for R6 calculates to 0.86 ohms. Using a standard

value 1.0 ohms resistor for R6, the ripple at VOUT ranges from

≊116 mVp-p to ≊1190 mVp-p over the input voltage range.

See Figure 11. If the application can accept this ripple level,

this is the most economical solution. The circuit is shown in

Figure 6.

30072013

FIGURE 6. Lowest Cost Configuration

Monitor The Inductor Current

The inductor’s current can be monitored or viewed on a scope

with a current probe. Remove the jumper from the WIRE

LOOP pads, and install an appropriate current loop across the

pads. In this way the inductor’s ripple current and peak current

can be accurately determined.

Scope Probe Adapters

Scope probe adapters are provided on this evaluation board

for monitoring the waveform at the SW node, and at the

circuit’s output (VOUT), without using the probe’s ground lead

which can pick up noise from the switching waveforms. The

probe adapters are suitable for Tektronix P6137 or similar

probes, with a 0.135” diameter.

30072014

FIGURE 7. Complete Evaluation Board Schematic

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Bill of Materials

Item Description Mfg., Part Number Package Value

C1 Ceramic Capacitor United Chemicon

KTS101B685M55N0T00

2220 6.8 µF, 100V

C2 Ceramic Capacitor United Chemicon

KTS101B475M43N0T00

1812 4.7 µF, 100V

C3 Ceramic Capacitor TDK C2012X7R1C474K 0805 0.47 µF, 16V

C4 Ceramic Capacitor TDK C2012X7R2A102K 0805 1000 pF, 100V

C5 Ceramic Capacitor Unpopulated 0805

C6, C7 Ceramic Capacitor TDK C3225X5R0J476M 1210 47 µF, 6.3V

C8 Ceramic Capacitor TDK C2012X7R2A104K 0805 0.1 µF, 100V

C9 Ceramic Capacitor TDK C2012X7R2A103K 0805 0.01 µF, 100V

C10 Ceramic Capacitor TKD C2012X7R2A332K 0805 3300 pF, 100V

D1 Schottky Diode On Semi MBRB2060CT D2PAK 60V, 20A

L1 Power Inductor Wurth XXL 7447709150 12 mm x 12 mm x 10 mm 15 µH

Q1 P-Channel MOSFET Vishay Si7465DP SO-8 Power 60V, 5A

R1 Resistor Vishay CRCW08051002F 0805 10k

R2 Resistor Vishay CRCW08053401F 0805 3.4k

R3 Resistor Vishay CRCW08051911F 0805 1.91k

R4 Resistor Vishay CRCW08059092F 0805 90.9k

R5 Resistor Vishay WSL2010R0100F 2010 0.01 ohm,

R6 Resistor Vishay CRCW08050000Z 0805 0 ohms

R7 Resistor Vishay CRCW08052322F 0805 23.2k

U1 Switching Regulator National Semiconductor LM5085MY MSOP8-EP

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Circuit Performance

30072015

FIGURE 8. Efficiency vs Load Current

30072032

FIGURE 9. Efficiency vs Input Voltage

30072017

FIGURE 10. Switching Frequency vs. Input Voltage

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30072018

FIGURE 11. Output Voltage Ripple

30072030

FIGURE 12. Line Regulation

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30072031

FIGURE 13. Load Regulation

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Typical Waveforms

30072019

Trace 4 = Inductor Current

Trace 1 = VOUT

Trace 2 = SW Node

VIN = 48V, IOUT = 1Amp

Minimum Ripple Configuration (Option A)

FIGURE 14. Continuous Conduction Mode

30072020

Trace 4 = Inductor Current

Trace 1 = VOUT

Trace 2 = SW Node

VIN = 48V, IOUT = 0

FIGURE 15. Discontinuous Conduction Mode

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30072021

Trace 4 = Inductor Current

Trace 1 = VOUT

Trace 2 = SW Node

VIN = 48V, IOUT = 0

FIGURE 16. Discontinuous Conduction Mode (Expanded Scale)

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PC Board Layout

30072022

Board Silkscreen

30072023

Board Top Layer

30072024

Board Bottom Layer (Viewed from Top)

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Notes

AN-1878 LM5085 Evaluation Board

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