M29F080D70N6 - Numonyx - Product.Network

1/37September 2005

M29F080D

8 Mbit (1Mb x8, Uniform Block)

5V Supply Flash Memory

FEATURES SUMMARY

■SUPPLY VOLTAGE

–V

CC = 5V ±10% for PROGRAM, ERASE and

READ OPERATIONS

■ACCESS TIME: 55, 70, 90ns

■PROGRAMMING TIME

– 10µs per Byte typical

■16 UNIFORM 64Kbyte MEMORY BLOCKS

■PROGRA M/ERASE CONT ROLLER

– Embedded Byte Program algorithms

■ERASE SUSPEND and RESUME MODES

– Read and Program another Block during

Erase Suspend

■UNLOCK BYPASS PROGRAM COMMAND

– Faster Production/Batch Programming

■TEMPORARY BLOCK UNPROTECTION

MODE

■COMMON FLASH INTERFACE

– 64 bit Security Code

■LOW POWER CONSUMPTION

– Standby and Automatic Standby

■100,000 PROGRAM/ERASE CYCLES per

BLOCK

■ELECTRONIC SIGNATURE

– Manufactu rer Code : 20h

– Device Code: F1h

■ECOPACK® PACKAGES AVAILABLE

Figure 1. Packages

TSOP40 (N)

10 x 20mm

SO44 (M )

M29F080D

2/37

TABLE OF CONTENTS

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3. TSOP Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 4. SO Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 5. Block Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Address Inputs (A0-A19). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Reset/Block Temporary Unprotect (RP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

VCC Supply Voltage (5V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Special Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Block Protection and Blocks Unprotection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Table 2. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Read/Reset Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Unlock Bypass Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Unlock Bypass Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Unlock Bypass Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Chip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Block Erase Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Erase Suspend Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Erase Resume Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Read CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Block Protect and Chip Unprotect Commands.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 3. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3/37

M29F080D

Table 4. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . . 13

STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 5. Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 6. Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 7. Data Toggle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 6. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 7. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 8. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 9. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 8. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 9. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 10. Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 10. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 11. Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 11. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 12. Write AC Waveforms, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 12. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 13. Reset/Block Temporary Unprotect AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 13. Reset/Block Temporary Unprotect AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 22

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline . . . . . . . . . . . . . . . . 23

TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechanical Data . . . . . . . . 23

SO44 – 44 lead Plastic Small Outline, 525 mils body width, Package Outline. . . . . . . . . . . . . . . . 24

SO44 – 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data . . . . . . . . 24

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 14. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

BLOCK ADDRESS TABLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

APPENDIX A. BLOCK ADDRESS TABLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 15. Block Addresses, M29F080D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

APPENDIX B. COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

M29F080D

4/37

Table 16. Query Structure Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Table 17. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Table 18. CFI Query System Interface Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 19. Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Table 20. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 21. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

APPENDIX C. BLOCK PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

In-System Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 22. Pr ogra mmer Techniq ue Bus Ope rat io ns, BYT E = VIH or VIL . . . . . . . . . . . . . . . . . . . . . 31

Figure 14. Programmer Equipment Group Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 15. Programmer Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 16. In-System Equipment Group Protect Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 17. In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 23. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

5/37

M29F080D

SUMMARY DESCRIPTION

The M29F080D is a 8 Mbit (1Mb x8) non-volatile

memory that can be read, erased and repro-

grammed. These operations can be performed us-

ing a single low voltage 5V supply. On power-up

the memory defaults to its Read mode where it can

be read in the same way as a ROM or EPROM.

The memory is divided into 16 uniform blocks of

64Kbytes (see Figure 5, Block Addresses) that

can be erased independently so it is possible to

preserve valid data while old data is erased.

Blocks can be prot ected in groups of 4 to pr event

accidental Program or Erase commands from

modifying the memory. Program and Erase com-

mands are written to the Command Interface of

the memory. An on-chip Program/Erase Controller

simplifies the process of programming or erasing

the memory by taking care of all of the special op-

erations that are required to update the memory

contents. The end of a program or erase operation

can be detected and any error conditions identi-

fied. The command set required to control the

memory is consistent with JEDEC standards.

Chip Enable, Output Enable and Write Enable sig-

nals control the bus operation of the memory.

They allow simple connection to most micropro-

cessors, often without additional logic.

The memory is offered in TSOP40 (10 x 20mm) and

SO44 pac k age s. Access times of 55, 70 and 90ns

are available.

In order to meet environmental requirements, ST

offers the M29F080D in ECOPACK® packages .

ECOPACK packages are Lead-free. The category

of second Level Interconnect is marked on the

package and on the inner box label, in compliance

wit h JEDEC S tandar d JESD 97. The m aximum rat-

ings related to soldering conditions are also

marked on the inner box label.

ECOPACK is an ST trademark. ECOPACK speci-

fications are available at: www.st.com.

The memory is supplied with all the bits erased

(set to ’1’).

Figure 2. Logic Diagram Table 1. Signal Names

AI06141

A0-A19

DQ0-DQ7

VCC

M29F080D

VSS

A0-A19 Address Inputs

DQ0-DQ7 Data Inputs/Outputs

EChip Enable

GOutput Enable

WWrite Enable

RP Reset/Block Temporary Unprotect

RB Ready/Busy Output

VCC Supply Voltage

VSS Ground

NC Not Conn ect ed Internall y

M29F080D

6/37

Figure 3. TSOP Connections Figure 4. SO Connections

DQ1

DQ2A10

A4 A2

A14

A17

A18

DQ7

A13

A19

DQ5

DQ3

VSS

VCC

DQ4

DQ6

A12

A11

VCC

AI06142

M29F080D

20 21

A15

A16 G

VSS

DQ0

A17

A18

A19

A16

DQ6DQ2

VSS VCC

VSS DQ4

A13

RP VCC

A10

AI06143

M29F080D

2322

17DQ0

DQ1

DQ7

A15

A14

DQ3 21 DQ5

A11 A12

7/37

M29F080D

Figure 5. Block Addresses

Note: Also see Appendix A, Table 15 for a full listing of the Block Addresses.

AI06144

64 KByte

0FFFFFh

0F0000h

64 KByte

01FFFFh

010000h

64 KByte

00FFFFh

000000h

M29F080D

Block Addresses

0CFFFFh

Total of 16

64 KByte Blocks

64 KByte

0EFFFFh

0E0000h

0DFFFFh

0D0000h

64 KByte

020000h

02FFFFh

M29F080D

8/37

SIGNAL DESCRIPTIONS

See Figu re 2, L ogi c Di ag ra m, an d Tab le 1 , Si gn al

Names, for a brief overview of the signals connect-

ed to this device.

Address Inputs (A0-A19). The Address Inputs

select the cells in the memory array to access dur-

ing Bus Read operations. During Bus Write opera-

tions they control the commands sent to the

Command Interface of the internal state machine.

Data Inputs/Outputs (DQ0-DQ7). The Data I/O

outputs the data stored at the selected address

during a Bus Read operation. During Bus Write

operations they represent the commands sent to

the Command Interface of the internal state ma-

chine.

Chip Enable (E). The Chip Enable, E, activates

the memory, allowing Bus Read and Bus Write op-

erations to be performed. When Chip Enable is

High, VIH, all other pins are ignored.

Output Enable (G). The Output Enable, G, con-

trols the Bus Read operation of the memory.

Write Enable (W). The Writ e En a bl e, W, controls

the Bus Write operation of the memory’s Com-

mand Interface.

Reset/Block Temporary Unprotect (RP). The

Reset/Block Temporary Unprotect pin can be

us ed t o ap p ly a Ha r d wa r e R es et t o t he m e mo r y or

to tempora rily un prote ct a ll Bl oc k s that h av e be en

protected.

A Hardware Reset is achieved by holding Reset/

Block Temporary Unprotect Low, VIL, for at least

tPLPX. After Reset/Block Temporary Unprotect

goes High , VIH, the memory will be ready for Bu s

Read and Bus Write operations after tPHEL or

tRHEL, whichever occurs last. See the Ready/Busy

Output section, Table 13 and Figure 13, Reset/

Tem porary Unprotec t AC Characteristics for more

details.

Holding RP at VID will temporarily unprotect the

protected Blocks in the memory. Program and

Erase operations on all blocks will be possible.

The transition from VIH to VID must be slower than

tPHPHH.

Ready/Busy Output (RB). The Ready/Busy pin

is an open-drain output that can be used to identify

when the device is performing a Program or Erase

operation. During Program or Erase operations

Ready/Busy is Low, VOL. Ready/Busy is high-im-

pedance during Read mode, Auto Select mode

and Erase Suspend mode.

After a Hardware Reset, Bus Read and Bus Write

operations cannot begin until Ready/Busy be-

comes hi gh -impe dance. See Ta bl e 13 an d Fi gur e

13, Reset/Temporary Unprotect AC Characteris-

tics.

The use of an open-drain output allows the Ready/

Busy pins from several memories to be connected

to a single pull-up resistor. A Low will then indicate

that one, or more, of the memories is busy.

VCC Supply Voltage (5V). VCC provides the

power supply for all operations (Read, Program

and Erase).

The Command Interface is disabled when the VCC

Supply Voltage is less than the Lockout Voltage,

VLKO. This prevents Bus Write operations from ac-

cidentally damaging the data during power up,

power down and power surges. If the Program/

Erase Controller is programming or erasing during

this time then the operation aborts and the memo-

ry contents being altered will be invalid.

A 0.1µF capacitor should be connected between

the VCC Supply Voltage pin and the VSS Ground

pin to decouple the current surges from the power

supply, see Figure 10, AC Measurement Load Cir-

cuit. The PCB track widths must be sufficient to

carry the currents required during program and

erase operations, ICC3.

VSS Ground. VSS is the reference for all voltage

measurements.

9/37

M29F080D

BUS OPERATIONS

There are five standard bus operations that control

the device. Thes e are Bus Read, Bus Writ e, Out-

put Disable, Standby and Automatic Standby. See

Tables 2, Bus Operations, for a summary. Typical-

ly glitches of less than 5ns on Chip Enable or Write

Enable ar e ignored by the m emory an d do not af-

fect bus operations.

Bus Read. Bus Read operations read from the

memory cells, or specific registers in the Com-

mand Interface. A valid Bus Read operation in-

volves setting the desired address on the Address

Inputs, ap plyi ng a Low signal , V IL, to Ch ip E nab le

and Output Enable and keeping Write Enable

High, VIH. The Data Inputs /Outp uts wil l outpu t the

value, see Figure 10, Read Mode AC Waveforms,

and Table 10, Read AC Characteristics, for details

of when the output becomes valid.

Bus Write. Bus Write operations write to the

Command Interface. A valid Bus Write operation

begins by setting the desired address on the Ad-

dress Inputs. The Address Inputs are latched by

the Command Interface on the falling edge of Chip

Enable or Write Enable, whichever occurs last.

The Data Inpu ts/Ou tputs are l atched by the Com -

mand Interfa ce on the rising ed ge of Chip Enab le

or Write Enable, whichever occurs first. Output En-

able must rema in High , VIH, duri ng the whol e Bu s

Write operation. See Figures 11 and 12, Write AC

Waveforms, and Tables 11 and 12, Write AC

Characteristics, for details of the timing require-

ments.

Output Disable. The Data Inputs/Outputs are in

the high impedance state when Output Enable is

High, VIH.

Standby. When Chip Enable is High, VIH, the

memory enters Standby mode and the Data In-

puts/Outputs pins are placed in the high-imped-

ance state. To reduce the Supply Current to the

Standby Supply Current, ICC2, Chip Enable should

be held within VCC ± 0.2V. For the Standby current

level see Table 9, DC Characteristics.

During program or erase operations the memory

will continue to use the Program/Erase Supply

Current, ICC3, for Program or Erase operations un-

til the operation completes.

Automatic Standby. If CMOS levels (VCC ± 0.2V)

are used to drive the bus and the bus is inactive for

300ns or more the memory enters Automatic

Standby where the internal Supply Current is re-

duced to the Standby Supply Current, ICC2. The

Data Inputs/Outputs will still output data if a Bus

Read operation is in progress.

Special Bus Operations

Additional bus operations can be performed to

read the Electronic Signature and also to apply

and remove Block Protection. These bus opera-

tions are intende d for use by program ming eq uip-

ment and are not usually used in applications.

They require VID to be applied to some pins.

Electronic Signature. The memory has two

codes, the manufacturer code and the device

code, that can be read to identify the memory.

These cod es can b e read b y apply ing the s ignals

listed in Tables 2, Bus Operations.

Block Protection and Blocks Unprotection.

Blocks can be protected in groups of 4 against ac-

cidental Program or Erase. See Appendix A, Table

15, Block Addresses, for details of which blocks

must be p rotected togeth er a s a g roup. Pr otec ted

blocks can be unprotected to allow data to be

changed.

There are two methods available for protecting

and unprotecting the blocks, one for use on pro-

gramming equipment and the other for in-system

use. Blo ck P ro tect a nd Chi p Un pr otect operation s

are described in Appendix C.

Table 2. Bus Operations

Note: X = VIL or VIH.

Operation E G W Address Inputs

A0-A19 Data Inputs/Outputs

DQ7-DQ0

Bus Read VIL VIL VIH Cell Addre ss Data Outp ut

Bus Write VIL VIH VIL Command Address Data Input

Output Dis able X VIH VIH X Hi-Z

Standby VIH X X X Hi-Z

Read Manufacturer

Code VIL VIL VIH A0 = VIL, A1 = VIL, A9 = VID, Others

VIL or VIH 20h

Read De vice Code VIL VIL VIH A0 = VIH, A1 = VIL,

A9 = VID, Others VIL or VIH F1h

M29F080D

10/37

COMMAND INTERFACE

All Bus Write operations to the memory are inter-

preted by the Command Interface. Commands

consist of one or more sequential Bus Write oper-

ations. Failure to observe a valid sequence of Bus

Write operations will result in the memory return-

ing to Read mode. The long command sequences

are imposed to maximize data security.

Refer to Table 3, Commands, in conjunction with

the following text descriptions.

Read/Reset Command. The Read/Reset com-

mand returns the memory to its Read mode where

it behaves like a ROM or EPROM, unless other-

wise stated . It also resets the error s in the Status

can be used to issue the Read/Reset command.

The Read/Reset Command can be issued, be-

tween Bus Write cycles before the start of a pro-

gram or erase operation, to return the device to

read mod e. On ce th e progr am or erase oper ation

has started the Read/Reset command is no longer

accepted. The Read/Reset command will not

abort an Erase operation when issued while in

Erase Suspend.

Auto Select Command. The Auto Select com-

mand is u sed to read the M anufac turer Co de, the

Device Code and the Block Protection Status.

Three consecutive Bus Write operations are re-

quired to issue the Auto Select command. Once

the Auto Select command is issued the memory

remains in Auto Select mode until a Read/Reset

command is issued. Read CFI Query and Read/

Reset commands are accepted in Auto Select

mode, all other co mma nds are ignor ed.

From the Auto Select mode the Manufacturer

Code can be read using a Bus Read operation

with A0 = VIL and A1 = VIL. The other address bits

may be set to either VIL or VIH. The Manufacturer

Code for STMicroelectronics is 20h.

The Device Code can be read using a Bus Re ad

operation with A0 = VIH and A1 = VIL. The other

address bits may be set to either VIL or VIH. The

Device Code for the M29F080D F1h.

The Block Protection Status of each block can be

read using a Bus Read operation with A0 = VIL,

A1 = VIH, and A12-A19 specifying the address of

the block. The other address bits may be set to ei-

ther VIL or VIH. If the addressed block is protected

then 01h is output on Data Inputs/Outputs DQ0-

DQ7, otherwise 00h is o utput.

Program Command. The Program command

can be used to program a value to one address in

the memory array at a time. The command re-

quires four Bus Write operations, the final write op-

eration latches the address and data in the internal

state machine and starts the Program/Erase Con-

troller.

If the address falls in a protected block then the

Program command is ignored, the data remains

unchanged. The Status Register is never read and

no error condition is given.

During the p rogram op eration the memor y will ig-

nore all com mands . It is no t possib le to iss ue any

command to abort or pause the operation. Typical

program times are given in Table 4. Bus Read op-

erations during the program operation will output

the Status Register on the Data Inputs/Outputs.

See the section on the Status Register for more

details.

After the program operation has completed the

memory will return to the Read mode, unless an

error has occurred. When an error occurs the

memory will continue to output the Status Regis-

ter. A Read/Reset command must be issued to re-

set the error condition and return to Read mode.

Note that the Program command cannot change a

bit set at ’0’ back to ’1’. One of the Erase Com-

mands must be used to set all the bits in a block or

in the whole memory from ’0’ to ’1’.

Unlock Bypass Command. The Unlock Bypass

command is used in conjunction with the Unlock

Bypass Program command to program the memo-

ry. When the cycle time to the device is long (as

with some EPROM programmers) considerable

time saving can be made by using these com-

mands. Three Bus Write operations are required

to issue the Unlock Bypass command.

Once the Unlock Bypass command has been is-

sued the memory will only accept the Unlock By-

pass Program command and the Unlock Bypass

Reset command. The memory can be read as if in

Read mode.

Unlock Bypass Program Command. The Un-

lock Bypass Program command can be used to

program one address in the memory array at a

time. The com mand requir es two Bus Write oper -

ations, the final write operation latches the ad-

dress and data in the internal state machine and

starts the Program/Erase Controller.

The Program operation using the Unlock Bypass

Program command behaves identically to the Pro-

gram operation using the Program command. A

protected block cannot be pr og rammed; the oper-

ation cannot be aborted and the Status Register is

read. Errors must be reset using the Read/Reset

comma nd, which leaves the devi ce in Unlock By-

pass Mode. See the Program command for details

on the behavior.

Unlock Bypass Reset Command. The Unlock

Bypass Reset co mmand ca n be use d to retu rn to

Read/Reset mode from Unlock Bypass Mode.

Two Bus Write operations are required to issue the

Unlock Bypass Reset command. Read/Reset

11/37

M29F080D

command does not exit from Unlock Bypass

Mode.

Chip Erase Command. The Chip Erase com-

mand can be used to erase the entire chip. Six Bus

Write operations are required to issue the Chip

Erase Command and start the Program/Erase

Controller.

If any blocks are protected then these are ignored

and all the other blocks are erased. If all of the

blocks are protected the Chip Erase operation ap-

pears to start but will terminate within about 100µs,

leaving the da ta unc hanged . No err or con dition is

given when protected blocks are ignored.

During the erase operation the memory will ignore

all comman ds , inc lud in g the Eras e S usp end com -

mand. I t is not po ssible to iss ue any command to

abort the operation. Typical chip erase times are

given in Table 4. All Bus Read operations during

the Chip Erase operation will output the Status

tion on the Status Register for more details.

After the C hip Erase o peration has c om ple ted the

memory will return to the Read Mode, unless an

error has occurred. When an error occurs the

memory will continue to output the Status Regis-

ter. A Read/Reset command must be issued to re-

set the error condition and return to Read Mode.

The Chip Erase Command sets all of the bits in un-

protected blocks of the memory to ’1’. All previous

data is lost.

Block Erase Command. The Block Erase com-

mand can be used to erase a list of one or more

blocks. Six Bus Write operations are required to

select the first block in the list. Each additional

block in the list can be selected by repeating the

sixth Bus Write operation using the address of the

additiona l blo ck . The Bl oc k Er ase op er ati on st ar ts

the Program/Erase Controller about 50µs after the

last Bus Write operation. Once the Program/Erase

Controller starts it is not possible to select any

more blocks. Each additional block must therefore

be selected within 50µs of the last block. The 50µs

timer restarts when an additional block is selected.

The Status Register can be read after the sixth

Bus Write operation. See the Status Register sec-

tion for details on how to identify if the Program/

Erase Controller has started the Block Erase oper-

ation.

If any selected blocks are protected then these are

ignored and all the other selected blocks are

erased. If all of the selected blocks are protected

the Block Erase operation appears to start but will

terminate within about 100µs, leaving the data un-

changed. No error condition is given when protect-

ed blocks are ignored.

During the Bl ock Er ase o per at ion the memory will

ignore all commands except the Erase Suspend

comma nd. Typical block eras e times a re given in

Table 4. All Bus Read operations during the Block

Erase operation will output the Status Register on

the Data Inputs/Outputs. See the section on the

Status Register for more details.

After the Block Erase operation has completed the

memory will return to the Read Mode, unless an

error has occurred. When an error occurs the

memory will continue to output the Status Regis-

ter. A Read/Reset command must be issued to re-

set the error condition and return to Read mode.

The Block Erase Command sets all of the bits in

the unprotected selected blocks to ’1’. All previous

data in the selected blocks is lost.

Erase Suspe nd Co mmand . The Er as e S u sp en d

Command may be used to tempor arily suspend a

Block Erase operation and return the memory to

Read mode. The command requires one Bus

Write operation.

The Progra m/Erase Controlle r will suspen d with in

15µs of the Erase Suspend Command being is-

sued. Once the Program/Erase Controller has

stopped the memory will be set to Read mode and

the Erase will be suspended. If the Erase Suspend

command is issued during the period when the

memory is waiting for an additional block (before

the Program/Erase Controller starts) then the

Erase is su spended imme di atel y and wil l sta rt im -

mediately when the Erase Resume Command is

issued. It is not possible to select any further

blocks to erase after the Erase Resume.

M29F080D

12/37

During Erase Suspend it is possible to Read and

Program cells in blocks that are not being erased;

both Read and Program operations behave as

normal on these b locks. I f any attempt is mad e to

program in a protected bl ock or in the s uspended

block then the Program command is ignored and

the data remains unchanged. The Status Register

is not r ead and no error condit ion is given. Read -

ing from blocks that are being erased will output

the Status Register.

It is also possible to issue the Auto Select, Read

CFI Query and Unlock Bypass comman ds during

an Erase Suspend. The Read/Reset command

must be issued to return the device to Read Array

mode before the Resume command will be ac-

cepted.

Erase Resume Command. The Erase Resume

command must be used to restart the Program/

Erase Controller after an Erase Suspend. The de-

vice must be in Read Array mode before the Re-

sume command will be accepted. An erase can be

suspended and resumed more than once.

Read CFI Query Command. The Read CFI

Query Command is used to read data from the

Com mon Fl ash Inte rface (CFI ) Memo ry Ar ea. Th is

comma nd is val id when the devi ce is in the Re ad

Array mode, or when the device is in Autoselected

mode.

One Bus Write cycle is required to issue the Read

CFI Query Command. Once the command is is-

sued subs equent Bus Read operatio ns read fr om

the Common Flash Interface Memory Area.

The Read/Reset command must be issued to re-

turn the device to the previous mode (the Read Ar-

ray mode or Autoselected mode). A second Read/

Reset com mand wo uld be needed if the d evice i s

to be put in the Read Array mode from Autoselect-

ed mode.

See Appendix B, Tables 16, 17, 18, 19, 20 and 21

for details on the information contained in the

Common Flash Interface (CFI) memory area.

Block Protect and Chip Unprotect Com-

mands. Groups of blocks can be protected

against ac ciden tal Pro gram or Er ase. T he Pro t ec-

tion Groups are shown in Appendix A, Table 15.

The whole chip can be unprotected to allow the

data inside the blocks to be changed.

Block Protect and Chip Unprotect operations are

described in Appendix C.

13/37

M29F080D

Table 3. Commands

Note: X Don’t C a r e, PA Program Address, PD Program Data, BA Any addres s in the Block . All values in the t able are in hexadecimal.

Table 4. Program, Erase Times and Program, Erase Endurance Cycles

Note: 1. TA = 25°C, VCC = 5V.

Command

Length

Bus Write Operations

1st 2nd 3rd 4th 5th 6th

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read/Reset 1X F0

3555 AA2AA 55 X F0

Auto Select 3 555 AA 2AA 55 555 90

Program 4 555 AA 2AA 55 555 A0 PA PD

Unlock Bypass 3 555 AA 2AA 55 555 20

Unlock Bypass

Program 2 X A0 PA PD

Unlock Bypass Reset 2 X 90 X 00

Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10

Block Erase 6+ 555 AA 2AA 55 555 80 55 5 AA 2AA 55 BA 30

Erase Suspend 1 X B0

Erase Resume 1 X 30

Read CFI Query 1 55 98

Parameter Min Typ (1) Typical after

100k W/E Cycles (1) Max Unit

Chip Erase 12 12 60 s

Block Erase (64 Kbytes) 0.8 6 s

Program (Byte) 10 200 µs

Chip Program (By te by Byte) 12 60 s

Program/Erase Cycles (per Block) 100,000 cycles

M29F080D

14/37

STATUS REGISTER

Bus Read operations from any address always

read the Status Register during Program and

Erase operations. It is also read during Erase Sus-

pend when an address within a block being erased

is accessed.

The bits in the S t atu s R egi st er ar e s umm ariz ed in

Table 5, Status Register Bits.

Data Polling Bit (DQ7). The Data P ollin g Bit can

be used to identify whether the Program/Erase

Controller has successfully completed its opera-

tion or if it has responded to an Erase Suspend.

The Data Polling Bit is output on DQ7 when the

Status Register is read.

During Program operations the Data Polling Bit

outputs the complement of the bit being pro-

grammed to DQ7. After successful completion of

the Program operation the memory returns to

Read mode and Bus Read operations from the ad-

dress just programmed output DQ7, not its com-

plement.

During Erase operations the Data Polling Bit out-

puts ’0’, the complement of the erased state of

DQ7. Afte r succe ssfu l com pleti on o f th e Era se op-

eration the memory returns to Read Mode.

In Erase Suspend mode the Data Polling Bit will

output a ’1’ during a Bus Rea d operation within a

block being erased. The Data Polling Bit will

change from a ’0’ to a ’1’ when the Program/Erase

Controller has suspended the Erase operation.

Figure 6, Data Polling Flowchart, gives an exam-

ple of how to use the Dat a Po lli ng Bit . A Va li d Ad -

dress is the address being programmed or an

address within the block being erased.

Toggle Bit (DQ6). The Toggle Bit can be used to

identify whether the Program/Erase Controller has

successfully completed its operation or if it has re-

sponded to an Erase Suspend. The Toggle Bit is

output on DQ6 when the Status Register is read.

During Prog ram a nd Eras e oper ations the Togg le

Bit change s from ’0’ to ’1’ to ’ 0’, etc. , with suc ces-

sive Bus Read operations at any address. After

successful completion of the operation the memo-

ry returns to Read mode.

During Erase Suspend mode the Toggle Bit will

output when addressing a cell within a block being

erased. The Toggle Bit will stop toggling when the

Program/Erase Controller has suspended the

Erase operation.

If any attemp t is mad e to e ra se a protec te d bl ock,

the operati on is aborted, n o error is signal led and

DQ6 toggles for approximately 100µs. If any at-

tempt is made to program a protected block or a

suspende d block, the opera tion is ab orted, no er -

ror is signalled and DQ6 toggles for approximately

1µs.

Figure 7, Data Toggl e Flowchart, gives an ex am-

ple of how to use the Data Toggle Bit.

Error Bit (DQ5). The Error Bit can be used to

identify errors detected by the Program/Erase

Controller. The Error Bit is set to ’1’ when a Pro-

gram, Block Erase or Chip Erase operation fails to

write the correct data to the memory. If the Error

Bit is set a Read/Res et comm and mus t be issu ed

before other commands are issued. The Error bit

is output on DQ5 when the Status Register is read.

Note that the Program command cannot change a

bit set to ’0’ back to ’1’ and attempting to do so will

set DQ5 to ‘1’. A Bus Read operation to that ad-

dress w il l show the bit is s ti ll ‘0’. One of the Erase

commands must be used to set all the bits in a

block or in the whole memory from ’0’ to ’1’.

Erase Ti m er B it (D Q3). The Eras e Timer Bit can

be used to identify the start of Program/Erase

Controller operation during a Block Erase com-

mand. Once the Program/Erase Controller starts

erasing the Erase Timer Bit is set to ’1’. Before the

Program/Erase Controller starts the Erase Timer

Bit is s et to ’0’ a nd additiona l block s to be eras ed

may be written to the Command Interface. The

Erase Timer Bit is output on DQ3 when the Status

Alternative Toggle Bit (DQ2). The Alternative

Toggle Bit can be used to monitor the Program/

Erase con troller d uring Erase o perations. T he Al-

ternative Toggle Bit is output on DQ2 when the

Status Register is read.

During Chip Erase and Block Erase operations the

Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with

successive Bus Read operations from addresses

within the bl ocks being eras ed. A protected bl ock

is treated the same as a block not being erased.

Once the operation completes the memory returns

to Read mode.

During Erase Suspend the Alternative Toggle Bit

changes from ’0’ to ’1’ to ’0’, etc. with successive

Bus Read operations from addresses within the

blocks be ing erased . Bus Read ope rations to ad -

dresses wi thi n b lock s not b eing e ra se d will out put

the memory cell data as if in Read mode.

After an E r ase o peration th at ca us es th e Er r or B it

to be set the Alternative Toggle Bit can be used to

identify which block or blocks have caused the er-

ror. The Alternative Toggle Bit changes from ’0’ to

’1’ to ’0’, etc. with successive Bus Read Opera-

tions from addresses within blocks that have not

erased correctly. The Alternative Toggle Bit does

not change if the addressed block has erased cor-

rectly.

15/37

M29F080D

Table 5. Status Register Bits

Note: Unspecified data bits should be ignored.

Figure 6. Data Polling Flowchart Figure 7. Data Toggle Flowchart

Operation Address DQ7 DQ6 DQ5 DQ3 DQ2 RB

Program Any Address DQ7 Toggle 0 – – 0

Program During Erase

Suspend Any Address DQ7 Toggle 0 – – 0

Program Err or Any Address D Q7 Toggle 1 – – 0

Chip Erase Any Address 0 Toggle 0 1 Toggle 0

Block Erase before

timeout Erasing Block 0 Toggle 0 0 Toggle 0

Non-Erasing Block 0 Toggle 0 0 No Toggle 0

Block Erase Erasing Block 0 Toggle 0 1 Toggle 0

Non-Erasing Block 0 Toggle 0 1 No Toggle 0

Erase Suspend Erasing Block 1 No Toggle 0 – Toggle 1

Non-Erasing Block Data read as normal 1

Erase Error Good Block Address 0 Toggle 1 1 No Toggle 0

Faulty Block Addre ss 0 To gg le 1 1 Toggle 0

READ DQ5 & DQ7

at VALID ADDRESS

START

READ DQ7

at VALID ADDRESS

FAIL PASS

AI05278

DQ7

DATA YES

YES

DQ5

= 1

DQ7

DATA YES

READ DQ6

START

READ DQ6

TWICE

FAIL PASS

AI05279

DQ6

TOGGLE NO

YES

DQ5

= 1

YES

DQ6

TOGGLE

READ

DQ5 & DQ6

M29F080D

16/37

MAXIMUM RATING

Stressing the dev ice abo ve the ratin g lis ted in the

Absolute Maximum Ratin gs table ma y cause pe r-

manent damage to the device. Expos ur e to Ab so -

lute Maximum Rating conditions for extended

periods may affect device reliability. These are

stress ratings only and operat ion of the device at

these or any other conditions above those indicat-

ed in the Operating sections of this specification is

not implied. Refer also to the STMicroelectronics

SURE Program and other relevant quality docu-

ments.

Table 6. Absolute Maximum Ratings

Note: 1. Minimum Voltage may undersh oot to –2V or ov ershoot to VCC +2V during transition for a maximum of 20ns.

Symbol Parameter Min Max Unit

TBIAS Temperature Under Bias –50 125 °C

TSTG Storage Temperature –65 150 °C

VIO Input or Output Voltage (1) –0.6 VCC + 0.6 V

VCC Supply Voltage –0.6 6 V

VID Identification Voltage –0.6 13.5 V

17/37

M29F080D

DC AND AC PARAMETERS

This section summarizes the operating measure-

ment condi tions, an d the DC and AC characteri s-

tics of the device. The parameters in the DC and

AC characteristics Tables that follow, are derived

from tests performed under the Measurement

Conditions summarized in Table 7, Operating and

AC Measurement Conditions. Designers should

check that the operati ng conditi ons in their circuit

match the operating conditions when relying on

the quoted parameters.

Table 7. Operating and AC Measurement Conditions

Figure 8. AC Measurement I/O Waveform Figure 9. AC Measurement Load Circuit

Tab le 8. Device Capacitance

Note: Sampled only, no t 100% tested.

Parameter

M29F080D

Unit55 70/ 90

Min Max Min Max

VCC Supply Voltage 4.5 5.5 4.5 5.5 V

Ambient Operating Temperature – 40 85 – 40 85 °C

Load Capacitance (CL)30 100 pF

Input Rise and Fall Times 10 10 ns

Input Pulse Voltages 0 to 3 0.45 to 2.4 V

Input and Output Timing Ref. Voltages 1.5 0.8 and 2.0 V

AI05276

High Speed (55ns)

1.5V

2.4V

Standard (70, 90ns)

0.45V

2.0V

0.8V

AI05277

1.3V

OUT

CL includes JIG capacitance

3.3kΩ

1N914

DEVICE

UNDER

TEST

VCC

0.1µF

Symbol Parameter Test Condition Min Max Unit

CIN Input Ca pa cita nc e VIN = 0V 6pF

COUT Output Capacitance VOUT = 0V 12 pF

M29F080D

18/37

Tab le 9. DC Characteristics

Note: 1. Sampled only, not 100% tested.

Symbol Parameter Test Condition Min Max Unit

ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±1 µA

ILO Output Leakage Current 0V ≤ VOUT ≤ VCC ±1 µA

ICC1 Supply Current (Read) E = VIL, G = VIH, f = 6MHz 20 mA

ICC2 Supply Current (Standby) TTL E = VIH 2mA

ICC3 Supply Current (Standby) CMOS E = VCC ± 0.2V,

RP = VCC ±0.2V 150 µA

ICC4 (1) Supply Current (Program/Erase) Program/Erase

Control ler ac tive 20 mA

VIL Input Low Voltage –0.5 0.8 V

VIH Input High Voltage 2 VCC + 0.5 V

VOL Output Low Voltage IOL = 5.8 mA 0.45 V

VOH Output High Voltage TTL IOH = –2.5mA 2.4 V

Output High Voltage CMOS IOH = –100µA VCC – 0.4 V

VID Identification Voltage 11.5 12.5 V

IID Identification Current A9 = VID 100 µA

VLKO (1) Progr am/Erase Lockout Supply

Voltage 3.2 4.2 V

19/37

M29F080D

Figure 10. Read AC Waveforms

Table 10. Read AC Characteristics

Note: 1. Sampled only, not 100% tested.

Symbol Alt Parameter Test Condition M29F080D Unit

55 70/ 90

tAVAV tRC Address Valid to Next Address Valid E = VIL,

G = VIL Min 55 70 ns

tAVQV tACC Address Valid to Output Valid E = VIL,

G = VIL Max 55 70 ns

tELQX (1) tLZ Chip Enable Low to Output Transition G = VIL Min 0 0 ns

tELQV tCE Chip Enable Low to Output Valid G = VIL Max 55 70 ns

tGLQX (1) tOLZ Output Enable Low to Output Transition E = VIL Min 0 0 ns

tGLQV tOE Output Enable Low to Output Valid E = VIL Max 30 30 ns

tEHQZ (1) tHZ Chip Enable High to Output Hi-Z G = VIL Max 18 20 ns

tGHQZ (1) tDF Output Enable High to Output Hi-Z E = VIL Max 18 20 ns

tEHQX

tGHQX

tAXQX tOH Chip Enable , Output Enable or Address

Transition to Output Transition Min 0 0 ns

AI06145

tAVAV

tAVQV tAXQX

tELQX tEHQZ

tGLQV

tGLQX tGHQX

VALID

A0-A19

DQ0-DQ7

tELQV tEHQX

tGHQZ

VALID

M29F080D

20/37

Figure 11. Write AC Waveforms, Write Enable Controlled

Table 11. Write AC Characteristics, Write Enable Controlled

Note: 1. Sampled only, not 100% tested.

Symbol Alt Parameter M29F080D Unit

55 70/ 90

tAVAV tWC Address Valid to Next Address Valid Min 55 70 ns

tELWL tCS Chip Enable Low to Write Enable Low Min 0 0 ns

tWLWH tWP Write Enable Low to Write Enable High Min 45 45 ns

tDVWH tDS Input Valid to Write Enable High Min 45 45 ns

tWHDX tDH Write Enable High to Input Transition Min 0 0 ns

tWHEH tCH Write Enable High to Chip Enable High Min 0 0 ns

tWHWL tWPH Write Enable High to Write Enable Low Min 20 20 ns

tAVWL tAS Address Valid to Write Enable Low Min 0 0 ns

tWLAX tAH Write Enable Low to Address Transition Min 45 45 ns

tGHWL Output Enable High to Write Enable Low Min 0 0 ns

tWHGL tOEH Write Enable High to Output Enable Low Min 0 0 ns

tWHRL (1) tBUSY Program/Erase Valid to RB Low Max 30 30 ns

tVCHEL tVCS VCC High to Chip Enable Low Min 50 50 µs

AI06146

A0-A19

DQ0-DQ7

VALID

VCC

tVCHEL

tWHEH

tWHWL

tELWL

tAVWL

tWHGL

tWLAX

tWHDX

tAVAV

tDVWH

tWLWHtGHWL

tWHRL

21/37

M29F080D

Figure 12. Write AC Waveforms, Chip Enable Controlled

Table 12. Write AC Characteristics, Chip Enable Controlled

Note: 1. Sampled only, not 100% tested.

Symbol Alt Parameter M29F080D Unit

55 70/ 90

tAVAV tWC Address Valid to Next Address Valid Min 55 70 ns

tWLEL tWS Write Enable Low to Chip Enable Low Min 0 0 ns

tELEH tCP Chip Enable Low to Chip Enable High Min 45 45 ns

tDVEH tDS Input Valid to Chip Enable High Min 45 45 ns

tEHDX tDH Chip Ena ble High to Inp ut Transit ion Min 0 0 ns

tEHWH tWH C hip Ena ble High to Write Enable High Min 0 0 ns

tEHEL tCPH Chip Enable High to Chip Enable Low Min 20 20 ns

tAVEL tAS Address Valid to Chip Enable Low Min 0 0 ns

tELAX tAH Chip Enable Low to Address Transition Min 45 45 ns

tGHEL Output Enable High Chip Enable Low Min 0 0 ns

tEHGL tOEH Chip Enable High to Output Enable Low Min 0 0 ns

tEHRL (1) tBUSY Program/Erase Valid to RB Low Max 30 30 ns

tVCHWL tVCS VCC High to Write Enable Low Min 50 50 µs

AI06147

A0-A19

DQ0-DQ7

VALID

VCC

tVCHWL

tEHWH

tEHEL

tWLEL

tAVEL

tEHGL

tELAX

tEHDX

tAVAV

tDVEH

tELEHtGHEL

tEHRL

M29F080D

22/37

Figure 13. Reset/Block Temporary Unprotect AC Waveforms

Table 13. Reset/Block Temporary Unprotect AC Characteristics

Note: 1. Sampled only, not 100% tested.

Symbol Alt Parameter M29F080D Unit

55 70/ 90

tPHWL (1)

tPHEL

tPHGL (1) tRH RP High to Wr ite Enable Low, Ch ip En able Low,

Output Enable Low Min 50 50 ns

tRHWL (1)

tRHEL (1)

tRHGL (1) tRB RB High to Wr ite Enable Low, Ch ip En able Low,

Output Enable Low Min 0 0 ns

tPLPX tRP RP Pulse Width Min 500 500 ns

tPLYH (1) tREADY RP Low to Read Mode Max 10 10 µs

tPHPHH (1) tVIDR RP Rise Time to VID Min 500 500 ns

AI02931B

RP tPLPX

tPHWL, tPHEL, tPHGL

tPLYH

tPHPHH

E, G

tRHWL, tRHEL, tRHGL

23/37

M29F080D

PACKAGE MECHANICAL

TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline

Note: Drawing is not to scale.

TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechanical Data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 1.200 0.0472

A1 0.050 0.150 0.0020 0.0059

A2 0.950 1.050 0.0374 0.0413

B 0.170 0.270 0.0067 0.0106

C 0.100 0.210 0.0039 0.0083

D 19.800 20.200 0.7795 0.7953

D1 18.300 18.500 0.7205 0.7283

E 9.900 10.100 0.3898 0.3976

e 0.500 – – 0.0197 – –

L 0.500 0.700 0.0197 0.0276

α0° 5° 0° 5°

N40 40

CP 0.100 0.0039

TSOP-a

1 N

N/2

DIE

LA1 α

M29F080D

24/37

SO44 – 44 lead Plastic Small Outline, 525 mils body width, Package Outline

Note: Drawing is not to scale.

SO44 – 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data

Symbol millimeters inches

Typ Min Max Typ Min Max

A2.800.1102

A1 0.10 0.0039

A2 2.30 2.20 2.40 0.0906 0.0866 0.0945

b 0.40 0.35 0.50 0.0157 0.0138 0.0197

C 0.15 0.10 0.20 0.0059 0.0039 0.0079

CP 0.08 0.0030

E 13.30 13.20 13.50 0.5236 0.5197 0.5315

D 28.20 28.00 28.40 1.1102 1.1024 1.1181

e 1.27 – – 0.0500 – –

HE 16.00 15.75 16.25 0.6299 0.6201 0.6398

L 0.80 0.0315

N44 44

α88

SO-d

LA1 α

eCP

25/37

M29F080D

PART NUMBERING

Table 14. Ordering Information Scheme

Devices are shipped from the factory with the memory content bits erased to ’1’.

For a lis t o f av aila ble option s (S pe ed, Pac kage , etc...) or for fu r ther i nfo rm ati on o n a ny aspec t o f th is de -

vice, please contact the ST Sales Office nearest to you.

Example: M29F080D 55 N 1 T

Device Type

M29

Operatin g Volt ag e

F = VCC = 5V ± 10%

Device Function

080D = 8 Mbit (1Mb x8), Uniform Block

Speed

55 = 55 ns

70 = 70 ns

90 = 90 ns

Package

N = TSOP40: 10 x 20 mm

M = SO44

Temperature Range

1 = 0 to 70 °C

6 = –40 to 85 °C

Option

Blank = Standard Packing

T = Tape & Reel Packing

E = ECOPACK Package, Standard Packing

F = ECOPACK Package, Tape & Reel Packing

M29F080D

26/37

APPENDIX A. BLOCK ADDRESS TABLE

Table 15. Block Addresses, M29F080D

#Size,

KByte Address Range Protection Group

15 64 0F0000h-0FFFFFh

14 64 0E0000h-0EFFFFh

13 64 0D0000h-0DFFFFh

12 64 0C0000h-0CFFFFh

11 64 0B0000h-0BFFFFh

10 64 0A0000h-0AFFFFh

9 64 090000h-09FFFFh

8 64 080000h-08FFFFh

7 64 070000h-07FFFFh

6 64 060000h-06FFFFh

5 64 050000h-05FFFFh

4 64 040000h-04FFFFh

3 64 030000h-03FFFFh

2 64 020000h-02FFFFh

1 64 010000h-01FFFFh

0 64 000000h-00FFFFh

27/37

M29F080D

APPENDIX B. COMMON FLASH INTERFACE (CFI)

The Common Flash Interface is a JEDEC ap-

proved, standardized data structure that can be

read from the Flash memory device. It allows a

system so ftware to quer y the device to determine

various electrical and timing parameters, density

informati on and functions su pported by the mem-

ory. The system can interface easily with the de-

vice, en abl ing the software to u pgr ade it self when

necessary.

When the CF I Query Command is issued the de -

vice enters CFI Query mode and the data structure

is read from the memory. Tables 16, 17, 18, 19, 20

and 21 show the addresses used to retrieve the

data.

The CFI data structure also contains a security

area where a 64 bit unique security number is writ-

ten (see Table 21 , Secur ity Code ar ea ). This ar ea

can be accessed only in Read mode by the final

user. It is impo ssible to chang e the sec urity num -

ber after it has bee n written b y ST. Issu e a Read

command to return to Read mode.

Table 16. Query Structure Overview

Note: Query data are alway s presented on the lowest order data outputs.

Tab le 17. CFI Query Identification String

Address Sub-section Name Description

10h CFI Query Identification String Command set ID and algorithm data offset

1Bh System Interface Information Device timing & voltage information

27h Device Geometry Definition Flash device layout

40h Primary Algorithm-specific Extended Query

table Addition al infor m atio n spe cific to the Primary

Algor ith m (op tio na l)

61h Security Code Area 64 bit unique device number

Address Data Description Value

10h 51h "Q"

11h 52h Query Unique ASCII String "QRY" "R"

12h 59h "Y"

13h 02h Prim ary Alg ori th m Co mma n d Set an d Co nt r ol In t er face ID co de 16 bi t ID co de

defining a specific algorithm AMD

Compatible

14h 00h

15h 40h Address for Primary Algorithm extended Query table (see Table 19) P = 40h

16h 00h

17h 00h Alternate V endor Command Set and Control Interf ace ID Code second vendor

- specified algorithm supported NA

18h 00h

19h 00h Address for Alternate Algorithm extended Query table NA

1Ah 00h

M29F080D

28/37

Table 18. CFI Query System Interface Information

Note: 1 . Not supported in the CFI

Address Data Description Value

1Bh 45h VCC Logic Supply Minimum Program/Erase voltage

bit 7 to 4 BCD value in volts

bit 3 to 0 BCD value in 100 mV 4.5V

1Ch 55h VCC Logic Supply Maximum Program/Erase voltage

bit 7 to 4 BCD value in volts

bit 3 to 0 BCD value in 100 mV 5.5V

1Dh 00h VPP [Programming] Supply Minimum Program/Erase voltage

00h not supported NA

1Eh 00h VPP [Programming] Supply Maximum Program/Erase voltage

00h not supported NA

1Fh 04h Typical timeout per single byte program = 2n µs 16µs

20h 00h Typical timeout for minimum size write buffer program = 2n µs NA

21h 0Ah Typic al tim eo ut pe r indiv idu al block erase = 2n ms 1s

22h 00h Typic al tim eo ut for full chip erase = 2n ms see note (1)

23h 04h Maximum timeo ut for byte program = 2n times typica l 256µs

24h 00h Maximum timeout for write buffer program = 2n times typical NA

25h 03h Maximum timeout per individual block erase = 2n times typical 8s

26h 00h Maximum timeout for chip erase = 2n tim es typic al see note (1)

29/37

M29F080D

Table 19. Device Geometry Definition

Address Data Description Value

27h 14h Device Size = 2n in number of bytes 1 MByte

28h

29h 00h

00h Flash Device Interface Code description x8 only

Async.

2Ah

2Bh 00h

00h Maximum number of bytes in multi-byte program or page = 2n NA

2Ch 01h Number of Erase Block Regions within the device.

It specifies the number of region s within the device containing contiguous

Erase Blocks of the same size. 1

2Dh

2Eh 0Fh

00h Region 1 Information

Number of identical size erase block = 000Fh+1 16

2Fh

30h 00h

01h Region 1 Information

Block size in Region 1 = 0100h * 256 byte 64 Kbyte

M29F080D

30/37

Table 20. Primary Algorithm-Specific Extended Query Table

Table 21. Security Code Area

Address Data Description Value

40h 50h

Primary Algorithm extended Query table unique ASCII string “PRI”

"P"

41h 52h "R"

42h 49h "I"

43h 31h Major version number, ASCII "1"

44h 30h Minor version number, ASCII "0"

45h 00h Address Sensitive Unlock (bits 1 to 0)

00 = required, 01= not required

Silicon Revision Number (bits 7 to 2)

Yes

46h 02h Erase Suspend

00 = not supported, 01 = Read only, 02 = Read and Write 2

47h 04h Block Protection

00 = not supported, x = number of blocks per group 4

48h 01h Temporar y Block Unprotect

00 = not supported, 01 = supported yes

49h 04h Block Protect /Unprotect

04 = M29W400B mode 4

4Ah 00h Simultaneous Operations, 00 = not supported No

4Bh 00h Burst Mode, 00 = not supported, 01 = supported No

4Ch 00h Page Mode, 00 = not supported, 01 = 4 page word, 02 = 8 page word No

Address Data Description

61h XX

64 bit: unique de vice number

62h XX

63h XX

64h XX

65h XX

66h XX

67h XX

68h XX

31/37

M29F080D

APPENDIX C. BLOCK PROTECTION

Block protection can be used to prevent any oper-

ation from modifying the data stored in the memo-

ry. The blocks are protected in groups, refer to

Appendix A, Table 15 for details of the Protec tion

Groups. Once protected, Program and Erase op-

erations wit hin the protected group fail to change

the data.

There are three techniques that can be used to

control Block Protection, these are the Program-

mer technique, the In-System technique and Tem-

porary Unprotection. Temporary Unprotection is

controlled by the Reset/Block Temporary Unpro-

tection pi n, RP ; thi s is d es cribed i n th e Si gna l De -

scriptions section.

To protect the Extended Block issue the Enter Ex-

tended Block command and then use either the

Programmer or In-System technique. Once pro-

tected iss ue the Exit Ext end ed Bl oc k co mma nd to

return to read mode. The Extende d Block protec -

tion is irreversible, once protected the protection

cannot be undone.

Programmer Technique

The Programmer technique uses high (VID) volt-

age levels on some of the bus pins. These cannot

be achieved using a standard microprocessor bus,

therefore the technique is recommended only for

use in Prog ramming Equipment.

To protect a group of blocks follow the flowchart in

Figure 14, Programmer Equipment Block Protect

Flowchart. To unprotect the whole chip it is neces-

sary to protect all of the groups first, then all

groups can be unprotected at the same time. To

unprotect the chip follow Figure 15, Programmer

Equipment Chip Unprotect Flowchart. Table 22,

Programmer Technique Bus Operations, gives a

summary of each operation.

The timing on these flowcharts is critical. Care

should be taken to ensure that, wher e a pause is

specifi ed, it is followe d as closely as possibl e. Do

not abort the procedure before reaching the end.

Chip Unprotect can take several seconds and a

user message should be provided to show that the

operation is progressing.

In-System Technique

The In-System technique requires a high voltage

level on the Reset/Blocks Temporary Unprotect

pin, RP. This can be achieved without violating the

maximum ratings of the components on the micro-

processor bus, therefore this technique is suitable

for use after the memory has been fitted to the sys-

tem.

To protect a group of blocks follow the flowchart in

Figure 16, In -System Bloc k Protect Flowc hart. To

unprotec t the whol e chi p it is nec ess ar y to prote ct

all of the groups first, then all the groups can be

unprotected at the same time. To unprotect the

chip follow Figure 17, In-System Chip Unprotect

Flowchart.

The timing on these flowcharts is critical. Care

should be taken to ensure that, wher e a pause is

specifi ed, it is followe d as closely as possibl e. Do

not allow the mi croproce ssor to servi ce interrupts

that will upset the timing and do not abor t the pro-

cedure before reaching the end. Chip Unprotect

can take several seconds and a user message

should be provided to show that the operation is

progressing.

Table 22. Programmer Technique Bus Operations, BYTE = VIH or VIL

Note: 1. B lock Protection Groups are shown in Appendix A, Table 15.

Operation E G W Address Inputs

A0-A19 Data Inputs/Outputs

DQ15A–1, DQ14-DQ0

Block (Group)

Protect(1) VIL VID VIL Pulse A9 = VID, A12-A19 Block Address

Others = X X

Chip Unpro te ct VID VID VIL Pulse A9 = VID, A12 = VIH, A15 = VIH

Others = X X

Block (Group)

Protection Verify VIL VIL VIH A0 = VIL, A1 = VIH, A6 = VIL, A9 = VID,

A12-A19 Block Address

Others = X

Pass = XX01h

Retry = XX00h

Block (Group)

Unprote cti on Ve r if y VIL VIL VIH A0 = VIL, A1 = VIH, A6 = VIH, A9 = VID,

A12-A19 Block Address

Others = X

Retry = XX01h

Pass = XX00h

M29F080D

32/37

Figure 14. Programmer Equipment Group Prote ct Flowchart

Note: Block Protection Groups are shown in Appendix A, Table 15.

ADDRESS = GROUP ADDRESS

AI05574

G, A9 = VID,

E = VIL

n = 0

Wait 4µs

Wait 100µs

W = VIL

W = VIH

E, G = VIH,

A0, A6 = VIL,

A1 = VIH

A9 = VIH

E, G = VIH

++n

= 25

START

FAIL

PASS

YES

DATA

01hYES

W = VIH

E = VIL

Wait 4µs

G = VIL

Wait 60ns

Read DATA

Verify Protect Set-upEnd

A9 = VIH

E, G = VIH

33/37

M29F080D

Figure 15. Programmer Equipment Chip Unprotect Flowchart

Note: Block Protection Groups are shown in Appendix A, Table 15.

PROTECT ALL GROUPS

AI05575

A6, A12, A15 = VIH(1)

E, G, A9 = VID

DATA

W = VIH

E, G = VIH

ADDRESS = CURRENT GROUP ADDRESS

A0 = VIL, A1, A6 = VIH

Wait 10ms

00h

INCREMENT

CURRENT GROUP

n = 0

CURRENT GROUP = 0

Wait 4µs

W = VIL

++n

= 1000

START

YES

YESNO

NO LAST

GROUP

YES

E = VIL

Wait 4µs

G = VIL

Wait 60ns

Read DATA

FAIL PASS

Verify Unprotect Set-upEnd

A9 = VIH

E, G = VIH A9 = VIH

E, G = VIH

M29F080D

34/37

Figure 16. In-System Equipment Group Protect Flowchart

Note: Block Protection Groups are shown in Appendix A, Table 15.

AI05576

WRITE 60h

ADDRESS = GROUP ADDRESS

A0 = VIL, A1 = VIH, A6 = VIL

n = 0

Wait 100µs

WRITE 40h

ADDRESS = GROUP ADDRESS

A0 = VIL, A1 = VIH, A6 = VIL

RP = VIH ++n

= 25

START

FAIL

PASS

YES

DATA

01hYES

RP = VIH

Wait 4µs

Verify Protect Set-upEnd

READ DATA

ADDRESS = GROUP ADDRESS

A0 = VIL, A1 = VIH, A6 = VIL

RP = VID

ISSUE READ/RESET

COMMAND

ISSUE READ/RESET

COMMAND

WRITE 60h

ADDRESS = GROUP ADDRESS

A0 = VIL, A1 = VIH, A6 = VIL

35/37

M29F080D

Figure 17. In-System Equipment Chip Unpr otect Flowchart

Note: Block Protection Groups are shown in Appendix A, Table 15.

AI05577

WRITE 60h

ANY ADDRESS WITH

A0 = VIL, A1 = VIH, A6 = VIH

n = 0

CURRENT GROUP = 0

Wait 10ms

WRITE 40h

ADDRESS = CURRENT GROUP ADDRESS

A0 = VIL, A1 = VIH, A6 = VIH

RP = VIH

++n

= 1000

START

FAIL PASS

YES

DATA

00h

YESNO

RP = VIH

Wait 4µs

READ DATA

ADDRESS = CURRENT GROUP ADDRESS

A0 = VIL, A1 = VIH, A6 = VIH

RP = VID

ISSUE READ/RESET

COMMAND

ISSUE READ/RESET

COMMAND

PROTECT ALL GROUPS

INCREMENT

CURRENT GROUP

LAST

GROUP

YES

WRITE 60h

ANY ADDRESS WITH

A0 = VIL, A1 = VIH, A6 = VIH

Verify Unprotect Set-upEnd

M29F080D

36/37

REVISION HISTORY

Table 23. Document Revision History

Date Version Revision De tai ls

03-Dec-2001 -01 First Issue

05-Apr-2002 -02 Descr i ptio n of Re ad y/B us y sign al cla r ifi ed (and Fig ur e 13 mo difi ed )

Clarified allowable commands during block erase

Clarified the mode the device returns to in the CFI Read Query command section

19-Sep-2005 3.0 Table 14. Ordering Information Scheme: standard package added and ECOPACK v ersion

added for both standard package and Tape & Reel packing.

Datasheet status changed to FULL DATASHEET.

37/37

M29F080D

Informatio n furnis hed is believ ed to be a ccurate and reli able. Howe ver, STMic roelectr onics assumes no r esponsib ility for th e consequences

of use of such inf ormation nor for any infringement of p atents or other rights of third part ies which may result fr om its use. No license is granted

by implication or otherwise under any patent or patent rig hts of STMicroelectronics. Specif ications ment ioned in this public ation are subject

to change wi thout notic e. T his pub licat ion su persed es and repl aces all info rmat ion previou sly su pplie d. STMicroele ctro nics prod ucts ar e no t

authorize d for use as critic al co mponents in life s upport devices or systems without express written approval of STMicroele ctr onics.

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