SMSC COM20020I Rev D Page 1 Revision 12-05-06
DATASHEET
COM20020I Rev D
5Mbps ARCNET (ANSI
878.1) Controller with
2K x 8 On-Chip RAM
Datasheet
Product Features
New Features for Rev. D
− Data Rates up to 5 Mbps
− Programmable Reconfiguration Times
28 Pin PLCC and 48 Pin TQFP Packages;
Lead-free RoHS Compliant P ackages also
Available
Ideal for Industrial/Factory/Building
Automation and Transportation Appl ications
Deterministic, (ANSI 878.1), Token Passing
ARCNET Protocol
Minimal Microcontroller and Medi a Interface
Logic Required
Flexible Interface For Use With All
Microcontrollers or Microproc essors
Automatically Detects Type of
Microcontroller Interface
2Kx8 On-Chip Dual Port RAM
Command Chaining for Packet Queuing
Sequential Access to Internal RAM
Software Programmable Node ID
Eight, 256 Byte Pages Allow Four Pages TX
and RX Plus Scratch-Pad Memory
Next ID Readable
Internal Clock Scaler and Clock Multiplier for
Adjusting Network Speed
Operating Temperature Ra nge of -40oC to
+85oC
Self-Reconfiguration Protocol
Supports up to 255 Nodes
Supports Various Network Topologies (Star,
Tree, Bus...)
CMOS, Single +5V Supply
Duplicate Node ID Detection
Powerful Diagnostics
Receive All Packets Mode
Flexible Media Interface:
− Traditional Hybrid Interface For Long
Distances up to Four Miles at 2.5 Mbps
− RS485 Differential Driver Interface For Low
Cost, Low Power, High Reliability
ORDERING INFORMATION
Order Numbers:
COM20020ILJP for 28 pin PLCC p ackage
COM20020I-DZD for 28 pin PLCC lead-free RoHS compliant package
COM20020I-HD for 48 pin TQFP package
COM20020I-HT for 48 pin TQFP lead-free RoHS compliant package
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Datasheet
Revision 12-05-06 Page 2 SMSC COM20020I Rev D
DATASHEET
80 Arkay Drive
Hauppauge, NY 11788
(631) 435-6000
FAX (631) 273-3123
Copyright © 2006 SMSC or its subsidiaries. All rights reserved.
Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete
information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no
responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without
notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does
not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC
or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard
Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors
known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request.
SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause
or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further
testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale
Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems
Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders.
SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLI ED WARRANTIES
OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND
ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY
DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR
REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC
OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO
HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
DAMAGES.
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Datasheet
SMSC COM20020I Rev D Page 3 Revision 12-05-06
DATASHEET
Table of Contents
Chapter 1 General Description................................................................................................................6
Chapter 2 Pin Configurations..................................................................................................................7
Chapter 3 Description of Pin Functions ..................................................................................................9
Chapter 4 Protocol Description.............................................................................................................12
4.1 Network Protocol........................................................................................................................................12
4.2 Data Rates.................................................................................................................................................12
4.2.1 Selecting Clock Frequencies Above 2.5 Mbps....................................................................................12
4.3 Network Reconfiguration............................................................................................................................13
4.4 Broadcast Messages..................................................................................................................................14
4.5 Extended Timeout Function .......................................................................................................................14
4.5.1 Response Time...................................................................................................................................14
4.5.2 Idle Time .............................................................................................................................................14
4.5.3 Reconfiguration Time..........................................................................................................................14
4.6 Line Protocol..............................................................................................................................................14
4.6.1 Invitations To Transmit........................................................................................................................15
4.6.2 Free Buffer Enquiries..........................................................................................................................15
4.6.3 Data Packets.......................................................................................................................................15
4.6.4 Acknowledgements.............................................................................................................................16
4.6.5 Negative Acknowledgements..............................................................................................................16
Chapter 5 System Description ..............................................................................................................17
5.1 Microcontroller Interface.............................................................................................................................17
5.1.1 High Speed CPU Bus Timing Support ................................................................................................20
5.2 Transmission Media Interf ace ....................................................................................................................21
5.2.1 Traditional Hybrid Interface.................................................................................................................21
5.2.2 Backplane Configuration.....................................................................................................................21
5.2.3 Differential Driver Configuration..........................................................................................................23
5.2.4 Programmable TXEN Polarity.............................................................................................................23
Chapter 6 Functional Description..........................................................................................................26
6.1 Microsequencer..........................................................................................................................................26
6.2 Internal Registers.......................................................................................................................................27
6.2.1 Interrupt Mask Register (IMR).............................................................................................................27
6.2.2 Data Register......................................................................................................................................28
6.2.3 Tentative ID Register ..........................................................................................................................28
6.2.4 Node ID Register.................................................................................................................................28
6.2.5 Next ID Register..................................................................................................................................28
6.2.6 Status Register....................................................................................................................................29
6.2.7 Diagnostic Status Register..................................................................................................................29
6.2.8 Command Register.............................................................................................................................29
6.2.9 Address Pointer Registers ..................................................................................................................29
6.2.10 Configuration Register.....................................................................................................................29
6.2.11 Sub-Address Register .....................................................................................................................29
6.2.12 Setup 1 Register..............................................................................................................................30
6.2.13 Setup 2 Register..............................................................................................................................30
6.3 Internal RAM ..............................................................................................................................................40
6.3.1 Sequential Access Memory.................................................................................................................40
6.3.2 Access Speed.....................................................................................................................................40
6.4 Software Interface......................................................................................................................................40
6.4.1 Selecting RAM Page Size...................................................................................................................41
6.4.2 Transmit Sequence.............................................................................................................................42
6.4.3 Receive Sequence..............................................................................................................................44
6.5 Command Chaining....................................................................................................................................45
6.5.1 Transmit Command Chaining .............................................................................................................45
6.5.2 Receive Command Chaining ..............................................................................................................46
6.6 Reset Details..............................................................................................................................................47
6.6.1 Internal Reset Logic............................................................................................................................47
6.7 Initialization Sequence ...............................................................................................................................47
6.7.1 Bus Determination...............................................................................................................................47
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
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6.8 Improved Diagnostics.................................................................................................................................48
6.8.1 Normal Results:...................................................................................................................................48
6.8.2 Abnormal Results:...............................................................................................................................48
6.9 Oscillator....................................................................................................................................................49
Chapter 7 Operational Description........................................................................................................50
7.1 Maximum Guaranteed Ratings* .................................................................................................................50
7.2 DC Electrical Characteristics......................................................................................................................50
Chapter 8 Timing Diagrams..................................................................................................................53
Chapter 9 Package Outlines.................................................................................................................66
Appendix A..................................................................................................................................................68
Appendix B - Example of Interface Circuit Diagram to ISA Bus.............................................................71
Appendix C - Software Identification of the COM20020 Rev B, Rev C and Rev D................................72
List of Figures
Figure 2.1 - Pin Configuration - COM20020I 28-Pin PLCC............................................................................................7
Figure 2.2 - Pin Configuration - COM20020I 48-Pin TQFP............................................................................................8
Figure 3.1 - COM20020ID Operation...........................................................................................................................11
Figure 5.1 – Multiplexed, 8051-Like Bus Interface with RS-485 Interface....................................................................18
Figure 5.2 – Non-Multiplexed, 6801-Like Bus Interface with RS-485 Interface............................................................19
Figure 5.3 – High Speed CPU Bus Timing – Intel CPU Mode......................................................................................20
Figure 5.4 - COM20020ID Network Using RS-485 Differential Transceivers...............................................................22
Figure 5.5 – Dipulse Waveform for Data of 1-1-0.........................................................................................................22
Figure 5.6 - Internal Block Diagram..............................................................................................................................24
Figure 6.1 - Sequential Ac c ess O pe ration.....................................................................................................................39
Figure 6.2 - RAM Buffer Packet Configuration.............................................................................................................42
Figure 6.3 – Command Chaining Stat us Register Queue..............................................................................................44
Figure 8.1 – Multiplexed Bus, 68XX-Like Control Signals; Read Cycle........................................................................53
Figure 8.2 – Multiplexed Bus, 80XX-Like Control Signals; Read Cycle........................................................................54
Figure 8.3 - Multiplexed Bus, 68XX-Like Control Signals; Write Cycle.........................................................................55
Figure 8.4 - Multiplexed Bus, 80XX-Like Control Signals; Write Cycle.........................................................................56
Figure 8.5 - Non-Multiplexed Bus, 80XX-Like Control Signals; Read Cycle.................................................................57
Figure 8.6 - Non-Multiplexed Bus, 80XX-Like Control Signals; Read Cycle.................................................................58
Figure 8.7 - Non-Multiplexed Bus, 68XX-Like Control Signals; Read Cycle.................................................................59
Figure 8.8 - Non-Multiplexed Bus, 68XX-Like Control Signals; Read Cycle.................................................................60
Figure 8.9 - Non-Multiplexed Bus, 80XX-Like Control Signals; Write Cycle.................................................................61
Figure 8.10 - Non-Multiplexed Bus, 68XX-Like Control Signals; Write Cycle...............................................................62
Figure 8.11 - Normal Mode Transmit or Receive Timing..............................................................................................63
Figure 8.12 - Backplane Mode Transmit or Receive Timing ........................................................................................64
Figure 8.13 - TTL Input Timing on XTAL1 Pin..............................................................................................................65
Figure 8.14 - Reset and Interrupt Timing .....................................................................................................................65
Figure 9.1 - 28 Pin PLCC Package Dimensions...........................................................................................................66
Figure 9.2 - 48 Pin TQFP Package Outline..................................................................................................................67
Figure 0.1 - Effect of the EF Bit on the TA/RI Bit..........................................................................................................70
List of Tables
Table 5.1 - Typical Media.............................................................................................................................................24
Table 6.1 - Read Register Summary............................................................................................................................26
Table 6.2 - Write Register Summary............................................................................................................................27
Table 6.3 - Status Register...........................................................................................................................................31
Table 6.4 - Diagnostic S t atu s Re g ist er..........................................................................................................................32
Table 6.5 - Command R e g i ste r.....................................................................................................................................33
Table 6.6 - Address Pointe r High Register....................................................................................................................34
Table 6.7 - Address Pointe r Low Registe r.....................................................................................................................34
Table 6.8 - Sub Addre s s R eg i ste r.................................................................................................................................34
Table 6.9 - Configurati on Register................................................................................................................................35
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Datasheet
SMSC COM20020I Rev D Page 5 Revision 12-05-06
DATASHEET
Table 6.10 - Setup 1 Regis ter.......................................................................................................................................36
Table 6.11 - Setup 2 Regis ter.......................................................................................................................................37
Table 9.1 - 48 Pin TQFP Package Parameters............................................................................................................67
For more details on the ARCNET protocol en gine and traditi onal dipulse sign aling schemes, please re fer to the
ARCNET Local Area Network Standard, available from Standard Microsystems Corporation or the ARCNET
Designer's Handbook, available from Datapoint Corporation.
For more detailed inform atio n on ca bling op ti ons i nclu din g R S485, trans for m er-cou ple d RS-4 85 and Fiber Op tic
interfaces, please refer to the following technical note which is available from Standard Microsystems
Corporation: Technical Note 7-5 - Cabling Guidelines for the COM20020 ULANC.
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Datasheet
Revision 12-05-06 Page 6 SMSC COM20020I Rev D
DATASHEET
Chapter 1 General Description
SMSC's COM20020ID is a member of the family of Embedded ARCNET Controllers from Standard
Microsystems Corporation. The device is a general purpose communications controller for networking
microcontrollers and intelligent peripherals in industrial, automotive, and embedded control environments
using an ARCNET® protocol engine. The small 28 pin package, flexible microcontroller and media
interfaces, eight- page message support, and extended temperature range of the COM20020ID make it
the only true network controller optimized for use in industrial, embedded, and automotive applications.
Using an ARCNET protocol engine is the ideal solution for embedded control applications because it
provides a deterministic token-passing protocol, a highly reliable and proven networking scheme, and a
data rate of up to 5 Mbps when using the COM20020ID.
A token-passing protocol provides predictable response times because each network event occurs within a
predetermined time interval, based upon the number of nodes on the network. The deterministic nature of
ARCNET is essential in real time applications. The integration of the 2Kx8 RAM buffer on-chip, the
Command Chaining feature, the 5 Mbps maximum data rate, and the internal diagnostics make the
COM20020ID the highest performance embedded communications device available. With only one
COM20020ID and one microcontrol ler, a complete communications node ma y be implem ented.
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Datasheet
SMSC COM20020I Rev D Page 7 Revision 12-05-06
DATASHEET
Chapter 2 Pin Configurations
26
27
28
1
2
3
4
18
17
16
15
14
13
12
5678910
11
25 24 23 22 21 20 19
nPULSE 1
XTAL2
XTAL1
VDD
VSS
N/C
D7
nWR/DIR
nRD/nDS
VDD
A0/nMUX
A1
A2/ALE
AD0
nCS
nINTR
nRESET IN
VSS
nTXEN
RXIN
nPULSE2
AD1
AD2
VSS
D3
D4
D5
D6
Package: 28-Pin PLCC
COM20020 I LJP
PACKAGE TYPE: "LJP" = Standard (Sn/Pb) plated PLCC
"-DZD" = Pb-free plated PLCC
TEMP RANGE: (Blank) = Commercial = 0°C to +70°C
"I" = Industrial = -40°C to +85°C
DEVICE TYPE: 20020 = Universal Local Area Network Controller
(with 2K x 8 RAM)
Ordering Information:
Figure 2.1 - Pin Configuration - COM20020I 28-Pin PLCC
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Datasheet
Revision 12-05-06 Page 8 SMSC COM20020I Rev D
DATASHEET
Figure 2.2 - Pin Configu ratio n - COM20020I 48-Pin TQFP
48
47
46
45
44
43
42
41
40
39
38
37
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
N/C
N/C
A2/ALE
A1
A0/nMUX
VDD
N/C
VSS
N/C
nRD/nDS
VDD
nWR/DIR
D7
N/C
N/C
N/C
N/C
VSS
N/C
VDD
XTAL1
XTAL2
VSS
nPULSE1
AD0
AD1
N/C
AD2
N/C
VSS
D3
VDD
D4
D5
VSS
D6
nCS
VDD
nINTR
N/C
VDD
nRESET
VSS
nTXEN
RXIN
N/C
BUSTMG
nPULSE2
COM20020I
48 PIN TQFP
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Datasheet
SMSC COM20020I Rev D Page 9 Revision 12-05-06
DATASHEET
Chapter 3 Description of Pin Functions
PLCC PIN
NO. NAME SYMBOL DESCRIPTION
MICROCONTROLLER INTERFACE
1-3 Address
0-2 A0/nMUX,
A1,A2/ALE Input. On a non-multiplexed mode, A0-A2 a re address
input bits. (A0 is the LSB) On a multiplexed address/data
bus, nMUX tied Low, A1 is left open, and ALE is tied to the
Address Latch Enable signal. A1 is connected to an internal
pull-up resistor.
4-6,8-12 Data 0-7 AD0-AD2, D3-D7 Input/Output. On a non-multiplexed bus, these signals are
used as the data lines for the device. On a multiple xed
address/data bus, AD0-AD2 act as the address lines
(latched by ALE) and as the low data lines for the device.
D3-D7 are always used for data only. These signals are
connected to internal pull-up r esistors.
27 nRead/nData
Strobe
nRD/nDS Input. On a 68XX-like bus, nDS is an active low signal
issued by the microcontroller as the data strobe signal to
strobe the data onto the bus. On a 80XX-like bus, nRD is
an active low signal issued by the microcontroller to
indicate a read operation.
26 nWrite/
Direction nWR/DIR Input. On a 68XX-like bus, DIR is issued by the
microcontroller as the Read/nWr ite signal to determine the
direction of data transfer. In this case, a logic "1" selects a
read operation, while a logic "0" selects a write operation.
In this case, data is actually strobed by the nDS signal. On
an 80XX-like bus, nW R is an active low signal issued by
the microcontroller to indicate a write operation. In this
case, a logic "0" on this pin, when the COM20020ID is
accessed, enables data from the data bus to be written to
the device.
23 nReset in nRESET Input. This active low signal executes a hardware res et.
24 nInterrupt nINTR
Output. This active low signal is generated by the
COM20020ID when an enabl ed interrupt condition occurs.
25 nChip Select nCS Input. This active low signal selects the COM20020ID for
an access.
TRANSMISSION MEDIA INTERFACE
19,18 nPulse 2,
nPulse 1 nPULSE2,
nPULSE1 Output (nPULSE1), Input/Output (nPULSE2). In Normal
Mode, these active low signals carry the transmit data
information, encoded in pulse format, as DIPULSE
waveform. When the device is in Backplane Mode, the
nPULSE1 signal driver is programmable (push/pull or open -
drain), while the nPULSE2 signal provides a clock with
frequency of double the data rate. nPULSE1 is connected
to a weak internal pull-up resistor on the open/drain driver
in backplane mode.
20 Receive In RXIN Input. This signal carries the receive data information from
the line transceiver.
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
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PLCC PIN
NO. NAME SYMBOL DESCRIPTION
21 nTransmit
nEnable nTXEN Output. This signal is used prior to the Power-up to enable
the line drivers for transmission. The polarit y of the signal
is programmable through the nPULSE2 pin.
nPULSE2 floating before Power-up: nT XEN active low
(Default option)
nPULSE2 grounded before Power-up: nTXEN active high
(This option is only availabl e in Backplane Mode)
16,17 Crystal
Oscillator XTAL1,
XTAL2 An external crystal should be connected to these p ins.
Oscillation frequency range is from 10 to 20 MHz. If an
external TTL clock is used ins t ead, it must be connected to
XTAL1 with a 390Ω pull- up resistor, and XTAL2 should be
left floating.
15,28 Power
Supply VDD +5 Volt Power Supply pin.
7,14,22 Ground VSS Ground pin.
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Datasheet
SMSC COM20020I Rev D Page 11 Revision 12-05-06
DATASHEET
Figure 3.1 - COM20020ID Operation
Invitation
to Transmit to
this ID?
YN
Free Buffer
Enquiry to
this ID? SOH?
YN
YN
RI?
Write SID
to Buffer
DID
=0?
DID
=ID?
Write Buf fer
with Packe t
CRC
OK?
LENGTH
OK?
DID
=0?
DID
=ID?
SEND ACK
N
Y
N
Y
N
YN
Broadcast
Enabled? N
Y
N
No Activity
for 41
uS?
Y
N
Set NI D=ID
Start Timer:
T=(255-ID)
Activity
On Line? Y
N
T=0?
Set RI
RI?
Transmit
NAK
Transmit
ACK
Set NID=ID
Write ID to
RAM Buffer
Send
Reconfigure
Burst
Powe r On
Reconfigure
Timer has
Timed Out
Start
Reconfiguration
Timer (420 mS)*
TA?
Broadcast? Transmit
Free Buffer
Enquiry No
Activity
Pass the
Token
Set TA
Y
N
ACK?
NAK?
1
No
Activity NY
Increment
NID
Send
Packet
Was Packet
Broadcast?
No
Activity
N
ACK? Set TMA
Set TA
x 73 us
for 37.4
us?
for 37.4
us?
for 37.4
us?
YN
N
Y
YN
NY
N
N
N
N
1
Y
Y
Y
YY
Y
Y
N
Y
Read Node ID
ID refers to the identificat i on number of the ID assigned to this node.
NID refers to the next identification number that receives the token
after this ID passes it.
-
-
-
-
SID refers to the source identification.
DID refers to the dest i nat i on identific at i on.
SOH refers to the star t o f head er ch aracter ; preceeds al l dat a packets.
-
YN
* Reconfig ti mer is pro gr ammable via setup2 register bits 1, 0.
Note - All time values are valid for 5 Mbps.
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
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Revision 12-05-06 Page 12 SMSC COM20020I Rev D
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Chapter 4 Protocol Description
4.1 Network Protocol
Communication on the network is based on a token passing protocol. Establishment of the network
configuration and m anageme nt of the net work protocol are handled entire ly by the COM2 0020ID's intern al
microcoded sequencer. A processor or intelligent peripheral transmits data by simply loading a data packet
and its destination ID into the COM20020ID's internal RAM buffer, and issuing a command to enable the
transmitter. When the COM2002 0ID next receives the tok en, it verifies tha t the receiving node is read y by
first transmitting a FREE BUFFER ENQUIRY message. If the receiving node transmits an ACKnowledge
message, the data packet is transmitted foll owed by a 16-bit CRC. If the receiving n ode c annot acce pt the
packet (typically its receiver is inhibited), it transmits a Negative AcKnowledge message and the
transmitter passes the token. Once it has b een established that the receiving node c an accept the pac ket
and transmission is complete, the receiving node verifies the packet. If the packet is received
successfully, the receiving node transmits an ACKnowledge message (or nothing if it is not received
successfully) allowing the transmitter to set the appropriate status bits to indicate successful or unsuccessful
delivery of the packet. An interrupt mask permits the COM20020ID to generate an interrupt to the processor
when selected status bits become true. Figure 3.1 is a flow chart illustrating the internal operation of the
COM20020ID connected to a 20 MHz crystal oscillator.
4.2 Data Rates
The COM20020ID is cap able of supporting data rates from 156.25 Kbps t o 5 Mbps. T he follo wing protocol
description assumes a 5 Mbps data rate. To attain the faster data rates, the clock frequency may be
doubled by the internal clock multiplier (see next section). For slower data rates, an internal clock divider
scales down the clock frequency. Thus all timeout values are scaled as shown in the following table:
Example:
IDLE LINE Timeout @ 5 Mbps = 41 μs. IDLE LINE Timeout for 156.2 Kbps is 41 μs * 32 = 1.3 ms
INTERNAL CLOCK
FREQUENCY CLOCK PRESCALER DATA RATE TIMEOUT SCALING FACTOR
(MULTIPLY BY)
40 MHz Div. by 8 5 Mbps 1
20 MHz Div. by 8
Div. by 16
Div. by 32
Div. by 64
Div. by 128
2.5 Mbps
1.25 Mbps
625 Kbps
312.5 Kbps
156.25 Kbps
2
4
8
16
32
4.2.1 Selecting Clock Frequencies Above 2.5 Mbps
To realize a 5 Mbps network, an external 40 MHz clock mus t be input. H owever, si nce 4 0 MHz is near th e
frequency of FM radio band, it is not practical for use for noise emission reasons.
Therefore, higher frequency clocks are generated from the 20 MHz cr ystal as selected through two bits in
the Setup2 register, CKUP[1,0] as shown below. The selected clock is supplied to the ARCNET controller.
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
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SMSC COM20020I Rev D Page 13 Revision 12-05-06
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CKUP1 CKUP0 CLOCK FREQUENCY (D ATA RATE)
0 0 20 MHz (Up to 2.5Mbps) Default (Bypass)
0 1 40 MHz (Up to 5Mbps)
1 0 Reserved
1 1 Reserved
This clock multiplier is powered-down (bypassed) on default. After changin g the CKUP1 and CKUP0 bits,
the ARCNET core operation is stopped and the internal PLL in the clock generator is awakened and it
starts to generate the 40 MHz. The lock out time of the internal PLL is 8uSec typically. After more than 8
μsec (this wait time is defined as 1 ms ec i n this dat a sh eet), it is nec essar y to write command data '18H' t o
the command register to re-start the ARCNET core operation. This clock generator is called “clock
multiplier”.
Changing the CKUP1 and C KUP0 bits must be one time or less after releasing hardware reset.
The EF bit in the SETUP2 register must be set when the data rate is over 5 Mbps.
4.3 Network Reconfiguration
A significant advantage of th e COM20020ID is its ability to adapt to c hanges on the network. Whenever a
new node is activated or deactivated, a NETWORK RECONFIGURATION is performed. When a new
COM20020ID is turned on (creating a new active node on the network), or if the COM20020ID has not
received an INVITATION TO TRANSMIT for 420mS, or if a software reset occurs, the COM20020ID
causes a NETWORK RECONFIGURATION by sending a RECONFIGURE BURST consisting of eight
marks and one space repeated 765 times. The purpose of this burst is to terminate all activity on the
network. Since this burst is longer tha n an y other t ype of transmission, th e burst will interfere with the next
INVITATION TO
TRANSMIT, destroy the token and keep any other node from assuming control of the line.
When any COM20020ID senses an idle line for greater than 41μS, which occurs only when the token Is
lost, each COM20020ID starts an internal timeout equal to 73μs times the quantit y 255 minus its own ID.
The COM20020ID starts net work reconfiguration b y sending an invitation to transmit first to itself and then
to all other nodes by decreme nting the desti nation Node ID. If the timeo ut expires with no line activity, the
COM20020ID starts sending INVITATION TO TRANSMIT with the Destination ID (DID) equal to the
currently stored NID. Within a given net work, only on e COM200 20ID will timeout (the on e with the highest
ID number). After sending the INVITATION TO TRANSMIT , the COM20020ID waits for activity on the line.
If there is no activity for 37.4μS, the COM20020ID increments the NID value and transmits another
INVITATION TO TRANSMIT using the NID equal to th e DID. If activit y appears before t he 37.4μS timeout
expires, the COM20020ID releases control of the line. During NETWORK RECONFIGURATION,
INVITATIONS TO TRANSMIT are sent to all NIDs (1-255).
Each COM20020ID on the net work will finally have save d a NID value equ al to the ID of the COM20020ID
that it released control to. At this point, control is passed dir ectly from one node to the next with no wasted
INVITATIONS TO TRANSMIT being sent to ID's not on the network, until the next NETWORK
RECONFIGURATION occurs. When a node is po wered off, the previous node attempts to pass the token
to it by issuing an INVITATION TO TRANSMIT. Since this node does not respond, the previous node
times out and transmits another INVITATION TO TRANSMIT to an incremented ID and eventually a
response will be received.
The NETWORK RECONFIGURATION time depends on the number of nodes in the network, the
propagation delay between nodes, and the highest ID number on the network, but is typically within the
range of 12 to 30.5 mS.
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
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4.4 Broadcast Messages
Broadcasting gives a particular node the ability to transmit a data packet to all nodes on the network
simultaneously. ID zero is reserved for this feature and no node on the n etwork can be assigned ID z ero.
To broadcast a message, the transmitting node's processor simply loads the RAM buffer with the data
packet and sets the DID equa l to zero. Figure 5.3 – High Speed CPU Bus Timing – Intel CPU M ode, pg.
20 illustrates the positio n of each byte in the packet with the DID residing at addr ess 0X01 or 1 Hex of the
current page selected in the "Enable Transmit from Page fnn" command. Each individual node has the
ability to ignore broadcast messages by setting the most sig nifica nt bit of the "Enable Receive to Pa ge fnn"
command to a logic "0".
4.5 Extended Timeout Function
There are three timeouts associated with the COM20020ID operation. The values of these timeouts are
controlled by bits 3 and 4 of the Configurati on Register and bit 5 of the Setup 1 Register.
4.5.1 Response Time
The Response Time determines the maximum propagation delay allowed between any two nodes, and
should be chosen to be larger than the round trip propagation delay between the two furthest nodes on
the network plus the maximum turn around time (the time it takes a particular COM20020ID to start
sending a message in response to a received message) which is approximately 6.4 μS. The round trip
propagation delay is a function of the transmission media and network topology. For a typical system
using RG62 coax in a baseband system, a one way cable propagation delay of 15.5 μS translates to a
distance of about 2 miles. The flow chart in Figure 3.1 uses a value of 37.4 μS (15.5 + 15.5 + 6.4) to
determine if any node will respond.
4.5.2 Idle Time
The Idle Time is associated with a NETWORK RECONFIGURATION. Figure 3.1 illustrates that during a
NETWORK RECONFIGURATION one node will contin ually transmit INVITATIONS TO TRANSMIT until it
encounters an active node. All other nodes on the network must distinguis h bet ween this operation a nd an
entirely idle line. During NETWORK RECONFIGURATION, activity will appear on the line every 41 μS.
This 41 μS is equal to the Response Time of 37.4 μS plus the time it takes the COM20020ID to start
retransmitting another message (usually another INVITATION TO TRANSMIT).
4.5.3 Reconfiguration Time
If any node does not receive the token within the Reconfiguration T ime, the node will init iate a NETWORK
RECONFIGURATION. The ET2 and ET1 bits of the Configuration Register allow the network to operate
over longer distances than the 2 miles stated earlier. The logic levels on these bits control the maximum
distances over which the COM20020ID can operate by controlling the three timeout values described
above. For proper network operation, all COM20020ID's connected to the same network must have the
same Response Time, Idle T ime, and Reconfiguration Time.
4.6 Line Protocol
The ARCNET line protocol is considered isochronous because each byte is preceded by a start interval
and ended with a stop interval. Unlike asynchronous protocols, there is a constant amount of time
separating each data byte. On a 5 Mbps network, each byte takes exactly 11 clock intervals of 200ns
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
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SMSC COM20020I Rev D Page 15 Revision 12-05-06
DATASHEET
each. As a result, one byte is transmitted every 2.2 μS and the time to transmit a message can be
precisely determined. The line idles in a spacing (logic "0") condition. A logic "0" is defined as no line
activity and a logic "1" is defined as a negative pulse of 100nS duration. A transmission starts with an
ALERT BURST consisting of 6 unit intervals of mark (logic "1"). Eight bit data characters are then sent,
with each character preceded by 2 unit intervals of mark and one unit interval of space. Five types of
transmission can be performed as described bel ow:
4.6.1 Invitations To Transmit
An Invitation To Transmit is used to pass the token from o ne node to another and is sent by the following
sequence:
An ALERT BURST
An EOT (End Of Transmission: ASCII code 04H)
Two (repeated) DID (Destination ID) charact ers
ALERT
BURST EOT DID DID
4.6.2 Free Buffer Enquiries
A Free Buffer Enquiry is used to ask another node if it is able to accept a packet of data. It is sent by the
following sequence:
An ALERT BURST
An ENQ (ENQuiry: ASCII code 85H)
Two (repeated) DID (Destination ID) charact ers
ALERT
BURST ENQ DID DID
4.6.3 Data Packets
A Data Packet consists of the actual data being sent to another node. It is sent by the following sequence:
An ALERT BURST
An SOH (Start Of Header--ASCII code 01H)
An SID (Source ID) character
Two (repeated) DID (Destination ID) charact ers
A single COUNT character which is the 2's compleme nt of the numb er of da ta bytes to follow if a short
packet is sent, or 00H followed by a COUNT character if a long packet is sent.
N data bytes where COUNT = 256-N (or 512-N for a long packet)
Two CRC (Cyclic Redundancy Check) characters. The CRC polynomial used is: X16 + X15 + X2 + 1.
A
LERT
BURST SOH SID DID DID COUNT data data CRC CRC
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
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DATASHEET
4.6.4 Acknowledgements
An Acknowledgement is used to acknowledge reception of a packet or as an affirmative response to FREE
BUFFER ENQUIRIES and is sent by the following sequenc e:
An ALERT BURST
An ACK (ACKnowledgement--ASCII code 86H) character
ALERT BURST ACK
4.6.5 Negative Acknowledgements
A Negative Ackno wledgement is used as a negative response to FREE B UFFER ENQUIRIES and is sent
by the following sequence:
An ALERT BURST
A NAK (Negative Acknowledgement--ASCII code 15H) character
ALERT BURST NAK
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
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Chapter 5 System Description
5.1 Microcontroller Interface
The top halves of Figure 5.1 and Figure 5.2 illustrate typical COM20020ID interfaces to the
microcontrollers. T he interfaces consist of a 8-bit data bus, an address bus and a control bus. In order to
support a wide range of microcontrol lers without requiring glue logic and without increasing the num ber of
pins, the COM20020ID automatically detects and adapts to the type of microcontroller being used. Upon
hardware reset, the COM200 20ID first determines whether the read and writ e control signals are sep arate
READ and WRITE signals (like the 80XX) or DIRECTION and DATA STROBE (like the 68XX). To
determine the type of contro l sign als, the device re quires th e soft ware to execute at least one write access
to external memory before attempting to access the COM20020ID. The device defaults to 80XX-like
signals. Once the t ype of cont rol signals ar e deter mined, th e COM20020ID rema ins in th is interface m ode
until the next hardware reset occurs. The second determination the COM20020ID makes is whether the
bus is multiplexed or non-multiplexed. To determine the type of bus, the device requires the software to
write to an odd memory location follo wed by a read from an odd location before attempting to access the
COM20020ID. The signal on the A0 pi n during the odd location access tells the COM20020ID the type of
bus. Since multiplexed operation requires A0 to be active low, activity on the A0 line tells the
COM20020ID that the bus is non-multiplexed. The device defaults to multiplexed operation. Both
determinations may b e made simultaneousl y by performing a WRIT E followed by a READ operation t o an
odd location within the COM20020ID Address space 20020D registers. Once the type of bus is
determined, the COM20020ID remains i n this interface mode until hardware reset occurs.
Whenever nCS and nRD are activated, the preset determinations are assumed as final and will not be
changed until hardware reset. Refer to Description of Pin Functions section for details on the related
signals. All accesses to the internal RAM and the internal registers are controlled by the COM20020ID.
The internal RAM is accessed via a pointer-based scheme (refer to the Sequential Access Memory
section), and the internal registers are accessed via direct addressing. Many peripherals are not fast
enough to take advantage of high-speed microcontrollers. Since microcontrollers do not typically have
READY inputs, standard p eripherals cannot extend c ycles to extend the access time. The access time of
the COM20020ID, on the other hand, is so fast that it does not need to limit the speed of the
microcontroller. The COM20020ID is designed to be flexible so that it is i ndependent of the microcontroller
speed.
The COM20020ID provides fo r no wait state arbitration via direct addressing to its internal re gisters and a
pointer based addr essing scheme to access its internal RA M. The pointer may be us ed in auto-increme nt
mode for typical sequential buffer emptying or loading, or it can be taken out of auto-increment mode to
perform random accesses to the RAM. The data within the RAM is accessed through the data register.
Data being read is prefetched from memory and placed into the data register for the microcontroller to
read. It is important to notice that only by writing a new address pointer ( writing to an address pointer low),
one obtains the contents of COM20020I D int erna l RAM. Performing o nly read from th e D ata Register d oes
not load new data from the internal RAM. During a write operation, the data is stored in the data register
and then written into memory. Whenever the pointer is loaded for reads with a new value, data is
immediately prefetched to prepare for the first read operation.
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
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DATASHEET
Figure 5.1 – Multiplexed, 8051-Like Bus Interface with RS-485 In terface
RXIN
nPULSE
nPULSE
TXEN
GND
+5V
100
BACKPLANE
FIGURE A
RXIN
nPULSE
FIGURE B
Receive
HFD3212-
2
+5V
7
6
Transmitte
HFE4211-
+5V
3
2 Fiber
(ST
2
6
7
NOTE: COM20020 must be in backplane mode
A
D0-
nINT1
RESET
nRD
nWR
A
15
A
D0-AD2, D3-
nCS
nRESET
nRD/nD
nWR/DI
nINTR
A
2/BAL
A
LE
XTAL1
XTAL2
GND
RXIN
nPULSE
nPULSE
nTXEN
8051
COM20020ID
Differential
Configuratio
Media
may be
with Figure A, B or
*
75176B or
Equiv.
A
0/nMU
27 pF 27 pF
XTAL2
XTAL1
20 MH z
XTAL
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Datasheet
SMSC COM20020I Rev D Page 19 Revision 12-05-06
DATASHEET
Figure 5.2 – Non-Multiplexe d , 6801-Like Bus Interface with RS-485 Interface
D0-D7
nIRQ1
nRES
nIOS
R/nW
A
7
D0-D7
0/nMU
A
0
XTAL1
XTAL2
A
1
A
1
nCS
nRESET
nRD/nDS
nWR/nDIR
nINTR
A
2/BALE
A
2
RXIN
nPULSE1
nPULSE2
TXEN
GND
Differential Driver
Configuration
6801
COM20020ID
Media Interface
may be replaced
with Figure A, B or C.
*
75176B or
Equiv.
XTAL1 XTAL2
27 pF 27 pF
20MHz
XTAL
RXIN
nPULSE1
nPULSE2
nTXEN
GND
Traditional Hybrid
Configuration
RXIN
nPULSE1
nPULSE2
17, 19,
4, 13, 14
5.6K
1/2W
5.6K
1/2W
0.01 uF
1KV
12
11
-5V
0.47
uF 10
uF
+
3
0.47
uF
+
+5V
uF
10
6
FIGURE C
HYC9088
HYC9068 or
N/C
*Valid for 2.5 Mbps only.
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
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DATASHEET
5.1.1 High Speed CPU Bus Timing Support
High speed CPU bus support was added to the COM20020ID. The reasoning behind this is as follows:
With the Host interface in Non-multiplexed Bus mode, I/O address and Chip Select signals must be stable
before the read signal is acti ve and remain after the read signal is inactive. But the H igh Speed CPU bus
timing doesn't adhere to these timings. For example, a RISC type single chip microcontroller (like the
HITACHI SH-1 series) changes I/O address at the same time as the read signal. Therefore, several
external logic ICs would be required to connect to this microcontroller.
In addition, the Diagnostic Status (DIAG) register is cleared automatically by reading itself. The internal
DIAG register read signal is generated by decoding the Address (A2-A0), Chip Select (nCS) and Read
(nRD) signals. The decoder will generate a noise spike at the above tight timing. The DIAG register is
cleared by the spike signal without reading it self. This is u nexpected oper ation. Read ing the internal RAM
and Next Id Register have the same mechanism as reading the DIAG register.
Therefore, the address decode and host interface mode blocks were modified to fit the above CPU
interface to support high speed CPU bus timing. In Intel CPU mode (nRD, nWR mode), 3 bit I/O address
(A2-A0) and Chip Select (nCS) are sampled internally by Flip-Flops on the falling edge of the internal
delayed nRD signal. The internal real read signal is the more delayed nRD signal. But the rising edge of
nRD doesn't delay. By this modification, the internal real address and Chip Select are stable while the
internal real read signal is active. Refer to Figure 5.3 below.
Figure 5.3 – High Sp eed CPU Bus Timing – Intel CPU Mode
The I/O address and Chip Select signals, which are supplied to the data output logic, are not sampled.
Also, the nRD signal is not delayed, because the above sampling and delaying paths decrease the data
access time of the read cycle.
The above sampling and delaying signals are supplied to the Read Pulse Generation logic which
generates the clearing pulse for the Diagnostic register and generates the starting pulse of the RAM
Arbitration. Typical delay time between nRD and nRD1 is around 15nS and bet ween nRD1 and nRD2 is
around 10nS.
Longer pulse widths are needed due to these delays on nRD signal. However, the CPU can insert some
wait cycles to extend the width without any impact on performance.
The RBUSTMG bit was added to Disable/Enable the High Speed CPU Read function. It is defined as:
RBUSTMG=0, Disabled (Default); RBUSTMG=1, Enabled.
A2-A0, nCS
nRD
Delayed nRD
(nRD1)
Sampled A2-A0, nCS
More delayed nRD
(nRD2)
VALID
VALID
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
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DATASHEET
In the MOTOROLA CPU mode (DIR, nDS mode), the same modifications apply.
RBUSTMG BIT BUS TIMING MODE
0 Normal Speed CPU Read and Write
1 High Speed CPU Rea d and Normal Speed CPU Write
5.2 Transmission Media Interface
The bottom halves of Figure 5.1 and Figure 5.2 illustrate the COM20020ID interface to the transmission
media used to conn ect the node to the net work. Table 5.1 - Typical Medi a on page 24 lists different t ypes
of cable which are suitabl e for ARCNET appli cations. 1 T he user ma y interface to the cable of choice in on e
of three ways:
5.2.1 Traditional Hybrid Interface
The Traditional Hybrid Interface is that which is used with previous ARCNET devices. The Hybrid
Interface is recommended if the n ode is to b e pl aced in a n et work with other Hybrid-Interf aced no des. T he
Traditional Hybrid Interface is for use with nodes operating at 2.5 Mbps on ly. The transformer coupling of
the Hybrid offers isolation for the safety of the system and offers high Common Mode Rejection. The
Traditional Hybrid Interface us es circuits lik e SMSC's HYC9 068 or HYC90 88 to transfer t he pu lse- encoded
data between the ca ble and the COM20020ID. T he COM20020ID transmits a logic " 1" by generating t wo
100nSnon-overlapping negative pulses, nPULSE1 and nPULSE2. Lack of pulses indicates a logic "0".
The nPULSE1 and nPULSE2 sign als are sent to the Hybrid, which creates a 200nS dipulse signal on the
media. A logic "0" is transmitted by the absence of the dipulse. During reception, the 200nS dipulse
appearing on the media is coupled through the RF transformer of the LAN Driver, which produces a
positive pulse at the RXIN pin of the COM20020ID. The pulse on the RXIN pin represents a logic "1".
Lack of pulse represents a logic "0". Typically, RXIN pulses occur at multiples of 400nS. The
COM20020ID can tolerate distortion of plus or minus 100nS and still correctly capture and convert the
RXIN pulses to NRZ format. Figure 5.4 illustrates the events which occur in transmission or reception of
data consisting of 1, 1, 0.
Note: Please refer to TN7-5 – Cabling Guidelines for the COM20020 ULANC, available from SMSC, for
recommended cabling distance, termination, and node count for ARCNET nodes.
5.2.2 Backplane Configuration
The Backplane Open Drain Configuration is recommended for cost-sensitive, short-distance applications
like backplanes and instrumentation. T his mode is advant ageous bec aus e it saves components, cost, and
power.
Since the Backplane Configuration encodes data differently than the traditional Hybrid Configuration,
nodes utilizing the Backplane Configuration cannot communicate directly with nodes utilizing the
Traditional Hybrid Configuration. The Backplane Configuration does not isolate the node from the media
nor protects it from Common Mode noise, but Common Mode Noise is less of a problem in short
distances.
The COM20020ID supplies a programmable output driver for Backplane Mode operation. A push/pull or
open drain driver can be selected by progr amming the P1MODE bit of the Setup 1 Register (see register
descriptions for details). The COM20020I D defaults to an open drain output.
The Backplane Configuration provides for direct connection between the COM20020ID and the media.
Only one pull-up resistor (in open drain configuration of the output driver) is required somewhere on the
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Datasheet
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DATASHEET
media (not on each individual node). The nPULSE1 signal, in this mode, is an open drain or push/pull
driver and is used to directly drive the media. It issues a 200nS negative pulse to transmit a logic "1". Note
that when used in the open- drain mode, the COM20020ID does not have a fai l/safe input on the R XIN pin.
The nPULSE1 signal actually contains a weak pull-up resistor. This pull-up should not take the place of
the resistor required on the media for open drain mode.
Figure 5.4 - COM20020ID Network Using RS-485 Differential Transceivers
Figure 5.5 – Dipulse Waveform for Data of 1-1-0
In typical applications, the serial backplane is terminated at both ends and a bias is provided by the
external pull-up resistor.
The RXIN signal is directly connecte d to the cable vi a an internal Schmitt trigg er. A negative pulse on thi s
input indicates a logic "1". Lack of pulse indicates a logic "0". For typical single-ended backplane
applications, RXIN is connected to nPULSE 1 to make the serial backplane data line. A ground line (from
the coax or twisted pair) should run in parallel with the signal. For applications requiring different treatment
COM20020ID
+VCC
RBIAS +VCC +VCC
RBIAS RBIAS
RT RT
75176B or
Equiv.
COM20020ID COM20020ID
20MHZ
CLOCK
(FO R REF.
ONLY)
nPULSE1
nPULSE2
DIPULSE
RXIN
10
100ns
100ns
200ns
400ns
1
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
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DATASHEET
of the receive signal (like filtering or squelching), nPULSE1 and RXIN remain as independent pins.
External differential drivers/receivers for increased range an d common mode noise rejection, for exampl e,
would require the signals to be independent of one another. When the device is in Backplane Mode, the
clock provided by the nPULSE2 signal may be used for encoding the data into a different encoding
scheme or other synchronous operations needed on the serial data stream.
5.2.3 Differential Driver Configuration
The Differential Driver Configuration is a special case of the Backplane Mode. It is a dc coupled
configuration recommended for applications like car-area networks or other cost-sensitive applications
which do not require direct compatibility with existing ARCNET nodes and do not require isolation.
The Differential Driver Configuration cannot communicate directly with nodes utilizing the Traditional
Hybrid Configuration. Like the Backplane Configuration, the Differential Driver Configuration does not
isolate the node from the media.
The Differential Driver interface includes a RS485 Driver/Receiver to transfer the data between the cable
and the COM20020ID. The nPULSE1 signal transmits the data, provided the Transmit Enable signal is
active. The nPULSE1 signal issues a 2 00nS (at 2.5Mbps) negative pulse to transmit a logic "1". Lac k of
pulse indicates a l ogic "0". The R XIN signal receiv es the data, the transm itter portion of the COM20020I D
is disabled during reset an d the nPULSE1, nPULSE2 and nTXEN pins are inactive.
5.2.4 Programmable TXEN Polarity
To accommodate transceivers with active high ENABLE pi ns, the COM20020ID contains a programmable
TXEN output. To program the TXEN pin for an active high pulse, the nP ULSE2 pin should be connected
to ground. To retain the normal active low polarity, nPULSE2 should be left open. The polarity
determination is made at power on reset and is valid only for Backplane Mode operation. The nPULSE2
pin should remain grounded at all times if an active high pol arity is desired.
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
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DATASHEET
Figure 5.6 - Internal Block Diag ram
Table 5.1 - Typical Media
CABLE TYPE NOMINAL
IMPEDANCE ATTENUATION PER 1000 FT.
AT 5 MHZ
RG-62 Belden #86262 93Ω 5.5dB
RG-59/U Belden #89108 75Ω 7.0dB
RG-11/U Belden #89108 75Ω 5.5dB
IBM Type 1* Belden #89688 150Ω 7.0dB
IBM Type 3* Telephone Twisted Pair
Belden #1155A
100Ω
17.9dB
COMCODE 26 AWG Twisted Pair
Part #105-064-703
105Ω
16.0dB
*Non-plenum-rated cables of this type are also available.
MICRO-
SEQUENCER
AND
WORKING
REGISTERS
STATUS/
COMMAND
REGISTER
RESET
LOGIC
RECONFIGURATION
TIMER NODE ID
LOGIC
OSCILLATOR
TX/RX
LOGIC
ADDITIONAL
REGISTERS
ADDRESS
DECODING
CIRCUITRY 2K x 8
AD0-AD2,
BUS
ARBITRATION
CIRCUITRY
nPULSE1
nPULSE2
nTXEN
nINTR
nRESET
RAM
A0/nMUX
A1
A2/BALE
nRD/nDS
nWR/DIR
nCS
D3-D7
RXIN
XTAL1
XTAL2
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
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DATASHEET
Note: For more detailed information on Cabling options including RS-485, transformer-coupled RS-485 and Fiber
Optic interfaces, please refer to TN7-5 – Cabling Guidelines for the COM20020 ULANC, available from
Standard Microsystems Corporation.
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
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Revision 12-05-06 Page 26 SMSC COM20020I Rev D
DATASHEET
Chapter 6 Functional Description
6.1 Microsequencer
The COM20020ID contains an internal microsequencer which performs all of the control operations
necessary to carry out th e ARCNET protocol. It consis ts of a clock generator, a 544 x 8 ROM, a program
counter, two instruction registers, an instruction decoder, a no-op generator, jump logic, and
reconfiguration logic.
The COM20020ID derives a 10 MHz and a 5 MHz clock from the output clock of the Clock Multiplier.
These clocks provide the rate at which the instructions are executed within the COM20020ID. The 10
MHz clock is the rate at which the program co unter operates, while the 5 MHz clock is the rate at which the
instructions are executed. The microprogram is stored in the ROM and the instructions are fetched and
then placed into the instruction registers. One register holds the opcode, while the other holds the
immediate data. Once the in struction is fetched, it is decoded by the internal instructi on decoder, at which
point the COM20020ID proce eds to execute the instruction. When a no- op instruction is encountered, the
microsequencer enters a timed loop and the program counter is temporarily stopped until the loop is
complete. When a jump instruction is encountered, the program counter is loaded with the jump address
from the ROM. The COM20020ID contains an internal reconfiguration timer which interrupts the
microsequencer if it has timed out. At this point the pr ogram counter is cleared and the MYRECON bit of
the Diagnostic Status Register is set.
Table 6.1 - Read Register Summary
REGISTER MSB READ LSB ADDR
STATUS RI/TRI X/RI X/TA POR TEST RECON TMA TA/
TTA 00
DIAG.
STATUS MY-
RECON DUPID RCV-
ACT TOKEN EXC-
NAK TENTID NEW
NEXTID X 01
ADDRESS
PTR HIGH RD-
DATA AUTO-
INC X X X A10 A9 A8
02
ADDRESS
PTR LOW A7 A6 A5 A4 A3 A2 A1 A0 03
DATA D7 D6 D5 D4 D3 D2 D1 D0 04
SUB ADR (R/W)
Note 6.1 0 0 0 (R/W)
Note 6.1 SUB-
AD2 SUB-
AD1 SUB-
AD0 05
CONFIG-
URATION RESET CCHEN TXEN ET1 ET2 BACK-
PLANE SUB-
AD1 SUB-
AD0 06
TENTID TID7 TID6 TID5 TID4 TID3 TID2 TID1 TID0 07-0
NODE ID NID7 NID6 NID5 NID4 NID3 NID2 NID1 NID0 07-1
SETUP1 P1
MODE FOUR
NAKS X RCV-
ALL CKP3 CKP2 CKP1
SLOW-
ARB 07-2
NEXT ID NXT
ID7 NXT
ID6 NXT
ID5 NXT
ID4 NXT
ID3 NXT
ID2 NXT
ID1 NXT
ID0 07-3
SETUP2 RBUS-
TMG X CKUP1 CKUP0 EF NO-
SYNC RCN-
TM1 RCM-
TM2 07-4
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Note 6.1 (R/W) This bit can be Written or Read. For more information see Appendix C - Software
Identification of the COM20020 Rev B, Rev C and Rev D.
Table 6.2 - Write Register Summary
ADDR MSB WRITE LSB REGISTER
00 RI/TR1 0 0 0 EXCNAK
RECON NEW
NEXTID TA/
TTA INTERRUPT
MASK
01 C7 C6 C5 C4 C3 C2 C1 C0
COMMAND
02 RD-
DATA AUTO-
INC 0 0 0 A10 A9 A8
ADDRESS
PTR HIGH
03 A7 A6 A5 A4 A3 A2 A1 A0
ADDRESS
PTR LOW
04 D7 D6 D5 D4 D3 D2 D1 D0 DATA
05 (R/W)
Note 6.2 0 0 0
(R/W)
Note 6.2 SUB-
AD2 SUB-
AD1 SUB-
AD0 SUBADR
06 RESET CCHEN TXEN ET1 ET2 BACK-
PLANE SUB-
AD1 SUB-
AD0 CONFIG-
URATION
07-0 TID7 TID6 TID5 TID4 TID3 TID2 TID1 TID0 TENTID
07-1 NID7 NID6 NID5 NID4 NID3 NID2 NID1 NID0 NODEID
07-2 P1-
MODE FOUR
NAKS 0 RCV-
ALL CKP3 CKP2 CKP1
SLOW-
ARB SETUP1
07-3 0 0 0 0 0 0 0 0 TEST
07-4 RBUS-
TMG 0 CKUP1 CKUP0 EF NO-
SYNC RCN-
TM1 RCN-
TM0 SETUP2
Note 6.2 (R/W) This bit can be Written or Read. For more information see Appendix C - Software
Identification of the COM20020 Rev B, Rev C and Rev D.
6.2 Internal Registers
The COM20020ID contains 14 internal registers. Table 6.1 and Table 6.2 illustrate the COM20020ID
register map. All undefined bits are read as und efined and must be written as logic "0".
6.2.1 Interrupt Mask Register (IMR)
The COM20020ID is capable of generating an interrupt signal when certain status bits become true. A
write to the IMR specifies which status bits will be e nabled to generate an interrupt. The bit pos itions in the
IMR are in the same position as their corresponding status bits in the Status Register and Diagnostic
Status Register. A logic "1" in a particular position enables the corresponding interrupt. The Status bits
capable of generating an interrupt include the Receiver Inhibited bit, New Next ID bit, Excessive NAK bit,
Reconfiguration Timer bit, and Transmitter Available bit. No other Status or Diagnostic Status bits can
generate an interrupt.
The six maskable status bits are ANDed with their respective mask bits, and the results are ORed to
produce the interrupt signal. An RI or T A interrupt is masked when the corresponding mask bit is reset
to logic "0", but will reappear when the correspondin g mask bit is set to logic "1" ag ain, unless the interr upt
status condition has been cleared by this time. A RECON interrupt is cleared when the "Clear Flags"
command is issued. An EXCNAK interrupt is cleared when the "POR Clear Flags" command is issued. A
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
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New Next ID interrupt is cleared b y reading the Next ID Register. T he Interrupt Mask Register defaults to
the value 0000 0000 upon hardware reset.
6.2.2 Data Register
This read/write 8-bit register i s used as the channel through which the data to and from the RAM pass es.
The data is placed in or retrieved from the address location presently specified by the address pointer.
The contents of the Data Register are undefined upon hardware reset. In case of READ operation, the
Data Register is loaded with the contents of COM20020ID Internal Memory upon writing Address Pointer
low only once.
6.2.3 Tentative ID Register
The Tentative ID Register is a read/write 8-bit register accessed when the Sub Address Bits are set up
accordingly (please refer to the Configur ation Register and SUB ADR Register). The T entative ID Register
can be used while the node is on-line to build a network map of those nodes existing on the network. It
minimizes the need for operator interaction with the network. The no de determines the existence of other
nodes by placi ng a Node ID value i n the Tentative ID Register and waiting to see if the T entative ID bit of
the Diagnostic Status Register gets set. The network map developed by this method is only valid for a
short period of time, since nodes may join or depart from the network at any time. When using the
Tentative ID feature, a node cannot detect the existence of the next logical node to which it passes the
token. The Next ID Register will hold the ID value of that node. The Tentative ID Regist er defaults to the
value 0000 0000 upon hardware reset only.
6.2.4 Node ID Register
The Node ID Register is a read/write 8-bit register accessed when the Sub Address Bits are set up
accordingly (please refer to the Configuration Register and SUB ADR Register). The Node ID Register
contains the unique value which identifies this particular node. Each node on the network must have a
unique Node ID value at all times. The Duplicate ID bit of the Diagnostic Status Register helps the user
find a unique Node ID. Refer to the Initialization Sequence section for further detail on the use of the
DUPID bit. The core of the COM20020ID does not wake up until a Node ID other than z ero is written into
the Node ID Register. Duri ng this time, no microcode is e xecuted, no to kens are passed by this node, and
no reconfigurations are caused by this node. Once a non-zero NodeID is placed into the Node ID
Register, the core wakes up but will not join the n etwork until the T XEN bit of the Configuratio n Register is
set. While the Transmitter is disabled, the Receiv er portion of the device is still functiona l and will provide
the user with useful information about the network. T he Node ID Register defaults to the value 0000 0000
upon hardware reset only.
6.2.5 Next ID Register
The Next ID Register is an 8-bit, read-only register, accessed when the sub-address bits are set up
accordingly (please refer to the Configuration Register and SUB ADR Register). The Next ID Register
holds the value of the Node I D to which the COM20020ID will pass the token. W hen used in conjunction
with the Tentative ID Register, the Next ID Register can provide a complete network map. The Next ID
Register is updated each time a node e nters/leaves t he n etwork or when a network reconfiguration occu rs.
Each time the microsequencer updates the Next ID Register, a New Next ID interrupt is generated. This bit
is cleared by reading the Ne xt ID Register. Default value is 0000 0000 upon hardware or software reset.
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6.2.6 Status Register
The COM20020ID Status Register is an 8-bit read- only regi ster. All of the bits, except for bits 5 and 6, a re
software compatible with previous SMSC ARCNET devices. In previous SMSC ARCNET devices the
Extended Timeout status was provided in bits 5 and 6 of the Status Register. In the COM20020ID, the
COM20020, the COM90C66, and the COM90C165, COM20020-5, COM20051 and COM20051+ these
bits exist in and are controlle d by the Configuratio n Register. T he Status Register conte nts are defined a s
in Table 6.3, but are defined differently during the Command Chaining operation. Please refer to the
Command Chaining section for the defi nition of the Status Register during Command Cha ining operation.
The Status Register defaults to the value 1XX1 0001 upon either hardware or software reset.
6.2.7 Diagnostic Status Register
The Diagnostic Status R egister contains seven read-only bits which hel p the user troubleshoot the network
or node operation. Various combinations of these bits and the TXEN bit of the Configuration Register
represent different situations. All of these bits, except the Excessive NAcK bit and the New Next ID bit, are
reset to logic "0" upon reading the Diagnostic Status Register or upon software or hardware reset. The
EXCNAK bit is reset by the "POR Clear Flags" command or upon software or hardware reset. The
Diagnostic Status Register def aults to the value 0000 000X upon either hardware or software reset.
6.2.8 Command Register
Execution of commands are initiated by performing microcontroller writes to this register. Any
combinations of written data other than those listed in Table 6.4 are not permitted and may result in
incorrect chip and/or network operation.
6.2.9 Address Pointer Registers
These read/ write registers are each 8-bits wide and are used for addr essing the internal RAM. New pointer
addresses should be written by first writing to the High Register and then writing to the Low Register
because writing to the Low Register loa ds the address. The contents of the Address Pointer Hig h and Low
Registers are undefined upo n hardware reset. Writing to Address Pointer low loads the address.
6.2.10 Configuration Register
The Configuration Register is a read/write register which is used to configure the different modes of the
COM20020ID. The Configuration Register defaults to the value 0001 1000 upon hardware reset only.
SUBAD0 and SUBAD1 point to the selection in Register 7.
6.2.11 Sub-Address Register
The sub-address register is new to the COM20020ID, previously a reserved register. Bits 2, 1 and 0 are
used to select one of the registers assigned to address 7h. SUBAD1 and SUBAD0 already exist in the
Configuration register on th e COM20020B. They are e xactly same as those in th e Sub-Address r egister. If
the SUBAD1 and SUBAD0 bits in the Config uration register are cha nged, t he S UBAD1an d SUBA D0 in th e
Sub-Address register are also chan ged. SUBAD2 is a ne w sub-address b it. It Is used t o access the 1 ne w
Set Up register, SETUP2. This register is selected by setting SUBAD2=1. The SUBAD2 bit is cleared
automatically by writing the Configuration register.
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6.2.12 Setup 1 Register
The Setup 1 Register is a read/write 8-bit register accessed when the Sub Address Bits are set up
accordingly (see the bit definitions of the Co nfiguration Register). The Setup 1 Re gister allows the user to
change the network speed (data rate) or the arbitration speed independently, invoke the Receive All
feature and change the nPULSE1 driver type. The data rate may be slowed to 156.25Kbps and/or the
arbitration speed may be slowed by a factor of t wo. The Setup 1 Regist er defaults to the value 0000 0000
upon hardware reset only.
6.2.13 Setup 2 Register
The Setup 2 Register is new to the COM20 020ID. It is an 8 -bit read/write register accessed when the S ub
Address Bits SUBAD[2:0] are set up accordi ngly (se e the bit defi nitions of the S ub Addres s Register). T his
register contains bits for various functions. The CKUP1,0 bi ts select the clock to be gener ated from the 20
MHz crystal. The RBUSTMG bit is used to Disable/Enable Fast Read function for High Speed CPU bus
support. The EF bit is used to enable the new timing for certain functions in the COM20020ID (if EF = 0,
the timing is the same as in the COM20020 Rev. B). See Appendi x A. The NOSYNC bit is used to enable
the NOSYNC function during initialization. If this bit is reset, the line has to be idle for the RAM
initialization sequence to be written. If set, the line does n ot have to be idle for the in itialization sequence
to be written. See Appendix A, pg 68.
The RCNTM[1,0] bits are used to set the time-out period of the recon timer. Programming this timer for
shorter time periods has the benefit of shortened net work reconfiguration periods. T he time periods sho wn
in the table on the follo wing page are limited by a maxim um number of nodes in the net work. These time-
out period values are for 5Mbps. For other data rates, scale the time-out period time values accordingly;
the maximum node count remains the sam e.
RCNTM1 RCNTM0 TIME-OUT
PERIOD MAX NODE
COUNT
0 0 420 mS Up to 255 nodes
0 1 105 mS Up to 64 nodes
1 0 52.5 mS Up to 32 nodes
1 1 26.25 mS* Up to 16 nodes
Note 6.3
Note 6.3 The node ID value 255 must exist in the network for the 26.25 mS time-out to be valid.
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Table 6.3 - Status Register
BIT BIT NAME SYMBOL DESCRIPTION
7 Receiver
Inhibited RI This bit, if high, indicates that the receiver is not enabled because either
an "Enable Receive to Page fnn" command was never issued, or a packet
has been deposited into the R AM buffer page fnn as specified by the last
"Enable Receive to Page fnn" command. No messages will be received
until this command is issued, and once the message has been received,
the RI bit is set, thereby inhibiting the receiver. The RI bit is cleared by
issuing an "Enable Receive to Page fnn" command. This bit, when set,
will cause an interrupt if the corresponding bit of the Interrupt Mask
Register (IMR) is also set. When this bit is set and another s tation
attempts to send a packet to this station, this station will send a NAK.
6,5 (Reserved) These bits are undefined.
4 Power On Reset POR This bit, if high, indicates that the COM20020ID has been reset by either a
software reset, a hardware reset, or writing 00H to the Node ID Register.
The POR bit is cleared by the "Clear Flags" command.
3 Test TEST This bit is intended for test and diagnostic purposes. It is a logic "0" under
normal operating conditions.
2 Reconfiguration RECON This bit, if high, indicates that the Li ne Idle Timer has timed out because
the RXIN pin was idle for 41μS. The RECON bit is cleared during a "Clear
Flags" command. This bit, when set, will cause an interrupt if the
corresponding bit in the IMR is also set. The interrupt service routine
should consist of examining the MYRECON bit of the Diagnostic Status
Register to determine whether there are consecutive reconfigurations
caused by this node.
1
Transmitter
Message
Acknowledged
TMA This bit, if high, indicates that the packet transmitted as a result of an
"Enable Transmit from Page fnn" command has been acknowledged.
This bit should only be considered valid after the TA bit (bit 0) is set.
Broadcast messages are never acknowledged. The TMA bit is cleared by
issuing the "Enable Transmit from Page fnn" command.
0 Transmitter
Available TA This bit, if high, indicates that the transmitter is available for transmittin g.
This bit is set when the last byte of scheduled packet has been
transmitted out, or upon execution of a "D isable Transmitter" command.
The TA bit is cleared by issuing the "Enable Transmit from Page fnn"
command after the node next receives the token. This bit, when set, will
cause an interrupt if the corresponding bit in the IMR is also set.
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Table 6.4 - Diagnostic Status Register
BIT BIT NAME SYMBOL DESCRIPTION
7 My Reconfiguration MY-
RECON This bit, if high, indicates that a past reconfiguratio n was caused by this
node. It is set when the Lost Token Timer times out, and should be
typically read f ollowing an interrupt caused by RECON. Refer to the
Improved Diagnostics section for further detail.
6 Duplicate ID DUPID This bit, if high, indicates that the value in the Node ID Regist er matches
both Destination ID characters of the token and a response to this token
has occurred. Trailing zero's are also verified. A logic "1" on this bit
indicates a duplicate Node ID, thus the user should write a new value into
the Node ID Register. This bit is only useful for duplicate ID detection
when the device is off line, that is, when the transmitter is disabled. W hen
the device is on line this bit will be set every time the device gets the
token. This bit is reset automatically upon reading the D iagnostic Status
Register. Refer to the Improved Diagnostics section for further detail.
5 Receive
Activity RCVACT This bit, if high, indicates that data activity (logic "1") was detected on the
RXIN pin of the device. Refer to the Improved Diagnostics section for
further detail.
4 Token Seen TOKEN This bit, if high, indicates that a token h as been seen on the network, sent
by a node other than this one. Refer to the Improved Diagnostic section
for further detail.
3 Excessive NAK EXCNAK This bit, if high, indicates that either 128 or 4 Negative Ackno wledgements
have occurred in response to the F r ee Buffer Enquiry. This bit is cleared
upon the "POR Clear Flags" command. Reading the Diagnostic Status
Register does not clear this bit. T his bit, when set, will cause an interrupt
if the corresponding bit in the IMR is also set. Refer to the Improved
Diagnostics section for further detail.
2 Tentative ID TENTID This bit, if high, indicates that a response to a token whose DID matches
the value in the Tentative ID Register has occurred. The second DID and
the trailing zero's are not checked. Since each node sees every token
passed around the network, this feature can be used with the device on-
line in order to build and update a network map. Refer to the Improved
Diagnostics section for further detail.
1 New Next ID NEW
NXTID This bit, if high, indic ates that the Next ID Register has b ee n updated and
that a node has either joined or left the network. Reading the Diagnostic
Status Register does not clear this bit. This bit, when set, will cause an
interrupt if the corresponding bit in the IMR is also set. T he bit is cleared
by reading the Next ID Register.
1,0 (Reserved) These bits are undefined.
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Table 6.5 - Command Register
DATA COMMAND DESCRIPTION
0000 0000 Clear
Transmit
Interrupt
This command is used only in the Command Chaining operation. Please
refer to the Command Chaining section for definition of this command.
0000 0001 Disable
Transmitter This command will cancel any pending transmit command (t ransmission
that has not yet started) and will set the TA (Transmitter Available) status
bit to logic "1" when the COM20020ID next receives the token.
0000 0010 Disable
Receiver This command will cancel any pending receive command. If the
COM20020ID is not yet receiving a packet, the RI (Receiver Inhibited) bit
will be set to logic "1" the next time the token is received. If packet
reception is already und erway, reception will run to its normal
conclusion.
b0fn n100 Enable
Receive to
Page fnn
This command allows the COM20020ID to receiv e data packets into
RAM buffer page fnn and resets the RI status bit to logic "0". The values
placed in the "nn" bits indicate the page that the data will be receiv ed
into (page 0, 1, 2, or 3). If the value of "f" is a logic "1", an offset of 256
bytes will be added to that page specified in "nn", allowing a finer
resolution of the buffer. Refer to the Selecting RAM Page Size section
for further detail. If the value of "b" is logic "1", the device will also
receive broadcasts (transmissions to ID zero). The RI status bit is set to
logic "1" upon successful receptio n of a message.
00fn n011 Enable
Transmit from
Page fnn
This command prepares the COM200 20ID to begin a transmit sequence
from RAM buffer page fnn the next time it receives the token. The
values of the "nn" bits indicate which page to transmit from (0, 1, 2, or 3).
If "f" is logic "1", an offset of 256 bytes is the start of the page specified in
"nn", allowing a finer resolution of the buffer . Refer to the Selecting RAM
Page Size section for further detail. When thi s command is loaded, the
TA and TMA bits are reset to logic "0". The TA bit is set to logic "1" upon
completion of the transmit sequence. The TMA bit will hav e bee n set by
this time if the device has received an ACK from the destination node.
The ACK is strictly hardware level, sent by the receiving node before its
microcontroller is even aware of message reception. Refer to Figure 3.1
for details of the transmit sequence and its relation to the TA and TMA
status bits.
0000 c101 Define
Configuration This command defines the maximum length of packets that may be
handled by the device. If "c" is a logic "1", the device handles both long
and short packets. If "c" is a logic "0", the device handl es only short
packets.
000r p110 Clear Flags This command resets certain status bits of the COM20020ID. A logic "1"
on "p" resets the POR status bit and the EXCNAK Diagnostic status bit.
A logic "1" on "r" resets the RECON status bit.
0000 1000 Clear
Receive
Interrupt
This command is used only in the Command Chaining operation. Please
refer to the Command Chaining section for definition of this command.
0001 1000 Start Internal
Operation This command restarts the stopped interna l operation after changing
CKUP1 or CKUP0 bit.
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Table 6.6 - Address Pointer High Register
BIT BIT NAME SYMBOL DESCRIPTION
7 Read Data RDDATA This bit tells the COM20020ID whether the follo wing acces s will
be a read or write. A logic "1" prepares the device for a rea d, a
logic "0" prepares it for a write.
6 Auto Increment AUTOINC This bit controls whether the address pointer will increment
automatically. A logic "1" on this bit allows automatic increment of
the pointer after each access, while a logic "0" disables this
function. Please refer to the Sequential Access Memory section
for further detail.
5-3 (Reserved) These bits are undefined.
2-0 Address 10-8 A10-A8 These bits hold the upper three address bits which provide
addresses to RAM.
Table 6.7 - Address Pointer Low Register
BIT BIT NAME SYMBOL DESCRIPTION
7-0 Address 7-0 A7-A0
These bits hold the lo wer 8 address bits which provide the
addresses to RAM.
Table 6 .8 - Sub Address Register
BIT BIT NAME SYMBOL DESCRIPTION
7-3 Reserved These bits are undefined.
2,1,0 Sub Address 2,1,0 SUBAD
2,1,0
These bits determine which register at ad dress 07 may be
accessed. The combinations are as follows:
SUBAD2 SUBAD1 SUBAD0 Register
0 0 0 Tentative ID \ (Same
0 0 1 Node ID \ as in
0 1 0 Setup 1 / Config
0 1 1 Next ID / Register)
1 0 0 Setup 2
1 0 1 Reserved
1 1 0 Reserved
1 1 1 Reserved
SUBAD1 and SUBAD0 are exactly the same as exist in the
Configuration Regist er. SUBAD2 is cleared automatic all y by writing
the Configuration Register.
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Table 6.9 - Configuration Register
BIT BIT NAME SYMBOL DESCRIPTION
7 Reset RESET A software reset of the COM20020ID is executed by writing a logic
"1" to this bit. A software reset does not reset the microcontroller
interface mode, nor does it affect the Configuration Register. The
only registers that the software reset affect are the Status Register,
the Next ID Register, and the Diagnostic Stat us Register. This bit
must be brought back to logic "0" to release the reset.
6 Command
Chaining Enable CCHEN
This bit, if high, enables the Command Chaining operation of the
device. Please refer to the Command Chaining section for further
details. A low level on this bit ensures software compati bility with
previous SMSC ARCNET devices.
5 Transmit Enable TXEN When low, this bit disables transmissions by keeping nPULSE1,
nPULSE2 if in non-Backplane Mode, and nTXEN pin inactive.
When high, it enables the abo v e signals to be activated during
transmissions. This bit defaults low upon reset. This bit is typ ically
enabled once the Node ID is determined, and never disabled during
normal operation. Please r efer to the Improved Diagn ostics section
for details on evaluating network activity.
4,3 Extended
Timeout 1,2 ET1, ET2 These bits allow the network to oper ate over longer distances than
the default maximum 2 miles by control ling the Response, Idle, and
Reconfiguration T imes. All nodes should be configured with the
same timeout values for proper network oper ation. F or the
COM20020ID with a 20 MHz crystal osc illator, the bit combinations
follow:
ET2
0
0
1
1
ET1
0
1
0
1
Response
Time (μS)
596.6
298.4
149.2
37.4
Idle Time
(μS)
656
328
164
41
Reconfig
Time (mS)
840
840
840
420
Note: These values are for 5Mbps and RCNTMR[1,0]=00.
Reconfiguration time is changed by the RCNTMR1 and
RCNTMR0 bits.
2 Backplane BACK-
PLANE A logic "1" on this bit puts the device into Backplane Mode signalin g
which is used for Open Drain and Differential Driver interfaces.
1,0 Sub Address 1,0 SUBAD 1,0
These bits determine which register at ad dress 07 may be
accessed. The combinations are as follows:
SUBAD1 SUBAD0 Register
0 0 Tentative ID
0 1 Node ID
1 0 Setup 1
1 1 Next ID
See also the Sub Address Register.
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Table 6.10 - Setup 1 Register
BIT BIT NAME SYMBOL DESCRIPTION
7 Pulse1 Mode P1MODE This bit determines the type of PULSE1 output driver used in
Backplane Mode. When high, a push/pu ll output is used. When
low, an open drain output is used. The default is open drain.
6 Four NACKS FOUR
NACKS This bit, when set, will cause the EXNACK bit in the Diagnostic
Status Register to set after four NACKs to Free Buffer Enquiry are
detected by the COM20020ID. This bit, when reset, will set the
EXNACK bit after 128 NACKs to F r ee Buffer Enquiry. The default
is 128.
5 Reserved Do not set.
4 Receive All RCVALL This bit, when set, allows the COM20020ID to receive all va lid
data packets on the network, regardless of their destination ID.
This mode can be used to implement a network monitor with the
transmitter on- or off-line. Note that ACKs are only sent for
packets received with a destination ID equ al to the COM20020ID's
programmed node ID. This feature can be used to put the
COM20020ID in a 'listen-only' mode, where the transmitter is
disabled and the COM20020ID is not passing tokens. Defaults
low.
3,2,1 Clock Prescaler Bits
3,2,1 CKP3,2,1 These bits are used to determine the data rate of the
COM20020ID. The following table is for a 20 MHz crystal: (Clock
Multiplier is bypassed)
CKP3
0
0
0
0
1
CKP2
0
0
1
1
0
CKP1
0
1
0
1
0
DIVISOR
8
16
32
64
128
SPEED
2.5Mbs
1.25Mbs
625Kbs
312.5Kbs
156.25Kbs
NOTE: The lowest data rate achievable by the COM20020ID is
156.25Kbs. Defaults to 000 or 2.5Mbs. For Clock Multiplier output
clock speed greater than 20 MHz, CKP3, CKP2 and CKP1 must
all be zero.
0 Slow Arbitration
Select SLOWARB This bit, when set, will divide the arbitration clock b y 2. Mem ory
cycle times will increase when slow arbitration is selected.
NOTE: For clock multiplier output clock speeds greater than 40
MHz, SLOWARB must be set. Defaults to low.
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Table 6.11 - Setup 2 Register
BIT BIT NAME SYMBOL DESCRIPTION
7 Read Bus Timing
Select RBUSTMG This bit is used to Disable/Ena ble the High Speed CPU Read
function for High Speed CPU bus support. RBUSTMG=0: Disable
(Default), RBUSTMG=1: Enable. It does not influence write
operation. High speed CPU Read operation is only for non-
multiplexed bus.
6 Reserved This bit is undefined.
5,4 Clock Multiplier CKUP1, 0 Higher frequency clocks are generated from the 20 MHz crystal
through the selection of these two bits as shown. This clock
multiplier is powered-down on default. After changing the CK UP1
and CKUP0 bits, the ARCNET core operation is stopped and the
internal PLL in the clock multiplier is awakened and it starts to
generate the 40 MHz. The lock out time of the internal PL L is 8μSec
typically. After 1 mS it is necessary to write command data '18H' to
command register for re-starting the ARCNET core operation. EF
bit must be ‘1’ if the data rate is over 5Mbps.
CAUTION: Changing the CK UP1 and CKUP0 bits must be one
time or less after releasing a hardware reset.
CKUP1 CKUP0 Clock Frequency (Data Rate)
0 0 20 MHz (Up to 2.5Mbps) Default
0 1 40 MHz (Up to 5Mbps)
1 0 Reserved
1 1 Reserved
Note: After changing the CKUP1 or CKUP0 bits, it is nec essary to
write a command data '18H' to the command register.
Because after changing the CKUP [1, 0] bits, the internal
operation is stopped temporarily. The writing of the
command is to start the operation.
These initializing steps are shown below.
Hardware reset (Power ON)
Change CKUP[1, 0] bit
Wait 1mSec (wait until stable oscillation)
Write command '18H' (start internal operation)
Start initializing routine (Exec ute e xisting software)
3 Enhanced Functions EF This bit is used to enable the new enhanced functions in the
COM20020ID. EF = 0: Disable (Default), EF = 1: Enable. If EF = 0,
the timing and function is the same as in the COM20020, Revision
B. See Appendix A. EF bit must be ‘1’ if the data rate is over
5Mbps.
EF bit should be ‘1’ for new design customers.
EF bit should be ‘0’ for replacement customers.
2 No Synchronous NOSYNC This bit is used to enable the SYNC command during initial ization.
NOSYNC= 0, Enable (Default) T he line must be idle for the RAM
initialization sequence to be written. NOSYNC= 1, Disable:) The line
does not have to be idle for the RAM initialization sequence to be
written. See Appendix A.
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BIT BIT NAME SYMBOL DESCRIPTION
1,0 Reconfiguration Timer
1, 0 RCNTM1,0 These bits are used to program the reconfiguratio n timer as a
function of maximum node count. These bits set the time out perio d
of the reconfiguration timer as sho wn below. The time out periods
shown are for 5 Mbps.
RCNTM1 RCNTM0 Time Out Period Max Node Count
0 0 420 mS Up to 255 nodes
0 1 105 mS Up to 64 nodes
1 0 52.5 mS Up to 32 nodes
1 1 26.25 mS* Up to 16 nodes
Note*: The node ID value 255 must exist in the network for 26.25
mS timeout to be valid.
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Figure 6.1 - Sequential Access Operation
Address P ointer Register
Low
2K x 8
RAM
11
Data Register
8
I/O A dd res s 04 H
I/O A ddress 03H
11-Bit Counter
Memory
Address Bus
Memory
D a ta B us
D0-D7
High
I/O Address 02H
INTERNAL
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6.3 Internal RAM
The integration of the 2K x 8 RAM in the COM20020ID represents significant real estate savings. The
most obvious benefit is the 48 pin package in which the device is now placed (a direct result of the
integration of RAM). In addition, the PC board is now free of the cumbersome external RAM, external
latch, and multiplexed address/data bus and control functions which were necessary to interface to the
RAM. The integration of RAM represents significa nt cost savings because it isolates the system designer
from the changing costs of external RAM and it minimizes reliability problems, assembly time and costs,
and layout complexity.
6.3.1 Sequential Access Memory
The internal RAM is accessed via a pointer-based scheme. Rather than interfering with system memory,
the internal RAM is indirectl y accessed through the Ad dress High and Lo w Pointer Registers. T he data is
channeled to and from the microcontroller via the 8- bit data register. For example: a p acket in the int ernal
RAM buffer is read by the microcontroller by writing the corresponding address into the Address Pointer
High and Low Registers (offsets 02H and 03H). Note that the High Register should be written first,
followed by the Low Register, because writing to the Low Register loads the address. At this point the
device accesses that location and places the corresponding data into the data register. The
microcontroller then reads th e data register (offset 04H) to obtain the data at the specified location. If the
Auto Increment bit is set to logic "1", the device will automatically increment the address and place the
next byte of data into the data register, aga in to be read by the microc ontroller. This process is continued
until the entire pack et is read out of RAM. Refer to Figur e 6.1 for an illus tration of the Sequential Acc ess
operation. When switching between reads and writes, the pointer must first be written with the starting
address. At least one cycle time should separate the pointer being loaded and the first read (see timing
parameters).
6.3.2 Access Speed
The COM20020ID is able to accommodate very fast access cycles to its registers and buffers. Arbitration
to the buffer does not slow down the cycle because the pointer based access method allows data to be
prefetched from memory and stored in a temporary register. Likewise, data to be written is stored in the
temporary register and then written to memory.
For systems which do not require quick access time, the arbitration clock ma y b e slowed down by setting
bit 0 of the Setup1 Register equal to logic "1 ". Since the Slo w Arbitration f eature divides t he input cl ock b y
two, the duty cycle of the input clock may be relaxed.
6.4 Software Interface
The microcontroller interfaces to the COM200 20ID via software by accessi ng the various registers. T hese
actions are described in t he Internal Registers section. The soft ware flow for accessing the dat a buffer is
based on the Sequential Access scheme. The basic sequence is as follows:
Disable Interrupts
Write to Pointer Register High (specif ying Auto-Increment mode)
Write to Pointer Register Low (this loads the addr ess)
Enable Interrupts
Read or Write the Data Register (repeat as many times as necessary to empty or fill the buffer)
The pointer may now be read to determine how many transfers were completed.
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The software flow for controlling the Configuration, Node ID, Tentative ID, and Next ID registers is
generally limited to the initializ ation sequence and the maintenance of the network map.
Additionally, it is necessary to understand the details of how the other Internal Registers are used in the
transmit and receive sequences and to know how the internal RAM buffer is properly set up. The
sequence of events that tie these actions together is discussed as follows.
6.4.1 Selecting RAM Page Size
During normal operation, th e 2K x 8 of RAM is divided into four pa ges of 512 bytes each. The page to be
used is specified in the "Enable Transmit (Receive) from (to) Page fnn" command, where "nn" specifies
page 0, 1, 2, or 3. This allows the user to have constant control over the allocation of RAM.
When the Offset bit "f" (bit 5 of the "Enable Transmit (Receive) from (to) Page fnn" command word) is set
to logic "1", an offset of 256 bytes is added to the page specified. F or e xample: to transmit from the second
half of page 0, the c ommand "Enable Transmit from Page fnn" (fnn=100 in this case) is issued by writing
0010 0011 to the Command Register. This allows a finer resolution of the buffer pages without affecting
software compatibility. This scheme is useful for applications which frequently use packet sizes of 256
bytes or less, especially for microcontroller s ystems with limited memor y capacit y. The remaining portions
of the buffer pages which are not allocated for current transmit or receive packets may be used as
temporary storage for previo us network data, packets to be sent later, or as extra memor y for the system,
which may be indirectly acces s ed.
If the device is configured to handle both long and short packets (see "Define Configuration" command),
then receive pages shoul d al ways be 512 bytes lo ng bec ause th e user never kno ws what the length of the
receive packet will be. In this case, the transmit pages may be made 256 bytes long, leaving at least 512
bytes free at any given time. Even if the Command Chaining operation is being used, 512 bytes is still
guaranteed to be free because Command Chaining only requires two pages for transmit and two for
receive (in this case, two 256 byte pages for transmit and two 512 byte pages for receive, leaving 512
bytes free). Please note that it is the responsibility of software to reserve 512 bytes for each receive page if
the device is configured to handle long packets. The COM20020ID does not check page boundaries
during reception. If the device is configured to handle only short packets, then both transmit and receive
pages may be allocated as 25 6 bytes long, freeing at least 1KByte at any given time.
Even if the Command Chaining operation is being used, 1KByte is still guaranteed to be free because
Command Chaining only requires two pages for transmit and two for receive (in this case, a total of four
256 byte pages, leaving 1K free).
The general rule which ma y be applied to determine where in RAM a page begins is as follows:
Address = (nn x 512) + (f x 256).
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SID
DID
COU NT = 256-N
NOT USED
DATA BYTE 1
DATA BYTE 2
DATA BYTE N-1
DATA BYTE N
NOT USED
SID
DID
0
COUNT = 512-N
NO T USE D
DATA BYTE 1
DATA BYTE 2
DATA BYTE N-1
DATA BYTE N
SHORT PACKET
FORMAT LONG PACKET
FORMAT
A
DDRESS ADDRESS
0
1
2
COUNT
255
511
N = D ATA PA CKE T LENGTH
SID = SOURCE ID
DID = DESTINATION ID
(DID = 0 FOR BR OADCASTS)
0
1
2
COUNT
511
3
Figure 6.2 - RAM Buffer Packet Configuratio n
6.4.2 Transmit Sequence
During a transmit sequence, the microcontroller sele cts a 256 or 512 byte segment of the RAM buffer an d
writes into it. The appropriate buffer size is specified in the "Define Configuration" command. When long
packets are enabled, the COM20020ID interprets the packet as either a long or short packet, depending
on whether the buffer address 2 contains a zero or non-zero value. The format of the buffer is shown in
Figure 6.2. Address 0 contains the Source Identifier (SID); Address 1 contains the Destination Identifier
(DID); Address 2 (COUNT) contains, for short packets, the value 256-N, where N represents the number
of information bytes in the message, or for long packets, the value 0, indicating that it is indeed a long
packet. In the latter case, Address 3 (COUNT) would contain the value 512-N, where N represents the
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number of information b ytes in the message. T he SID in Address 0 is use d by the receivin g node to reply
to the transmitting node. T he COM20020ID puts the local I D in this location, therefore it is not necessa ry
to write into this location. Please note that a short packet may contain between 1 and 253 data bytes,
while a long packet may contain between 257 and 508 data bytes. A minimum value of 257 exists on a
long packet so that the COUNT is expressible in eight bits. This leaves three exception packet lengths
which do not fit into either a short or long packet; packet lengths of 254, 255, or 256 bytes. If packets of
these lengths must be sent, the user must add dummy bytes to the packet in order to make the packet fit
into a long packet.
Once the packet is written into the buffer, the microcontroller awaits a logic "1" on the TA bit, indicating that
a previous transmit command has concluded and another may be issued. Each time the message is
loaded and a transmit command issued, it will take a variable amount of time before the message is
transmitted, depending on the traffic on the network and the location of the token at the time the transmit
command was issued. The c onclusion of the T ransmit Command will generate an interrupt if th e Interrupt
Mask allows it. If the device is configure d for t he Comm an d Chai ni ng opera tion, pl eas e se e the Comman d
Chaining section for further detail on the transmit sequence. Once the TA bit becomes a logic "1", the
microcontroller may issue the "Enable Transmit from Page fnn" command, which resets the TA and TMA
bits to logic "0". If the message is not a BROADCAST, the COM20020ID automatically sends a FREE
BUFFER ENQUIRY to the destination node in order to send the message. At this point, one of four
possibilities may occur.
The first possibility is if a free buffer is availabl e at the destination node, in which case it responds with an
ACKnowledgement. At this point, the COM20020ID fetches the data from the Transmit Buffer and
performs the transmit sequence. If a successful transmit sequenc e is completed, the TMA bit and the TA
bit are set to logic "1". If the packet was not transmitted successfully, TMA will not be set. A successful
transmission occurs when the receiving node responds to the packet with an ACK. An unsuccessful
transmission occurs when the receiving node does not respond to the packet.
The second possibility is if the destination node responds to the Free Buffer Enquiry with a Negative
AcKnowledgement. A NAK occurs when the RI bit of the destination node is a logic "1". In this case, the
token is passed on from the t ransmitting node to the next node. T he next time the transmitter receiv es the
token, it will again transmit a FREE BUFFER ENQUIRY. If a NAK is again received, the token is again
passed onto the next node. The Excessive NAK bit of the Diagnostic Status Register is used to prevent an
endless sending of FBE's and NAK's. If no limit of FBE-NAK sequences existed, the transmitting node
would continue issuing a Free Buffer Enquiry, even though it would continuously receive a NAK as a
response. The EXCNAK bit generates an interrupt (if enabled) in order to tell th e microcontroller to disable
the transmitter via the "Disable Transmitter" command. This causes the transmission to be abandoned
and the TA bit to be set to a logic "1" when the node next receives the token, while the TMA bit remains at
a logic "0". Please refer to the Improved Diagnostics section for further detail on the EXCNAK bit.
The third possibilit y which may occur after a FREE BUFFER ENQUIRY is issued is if the destination nod e
does not respond at all. In this case, the TA bit is set to a logic "1", while the TMA bit remains at a logic
"0". The user should determine whether the node should try to reissue the transmit command.
The fourth possibility is if a non-traditional response is received (some pattern other than ACK or NAK,
such as noise). In this case, the token is not passed onto the next node, which causes the Lost Token
Timer of the next node to time out, thus generating a network reconfiguration.
The "Disable Transmitter" command may be used to cancel any pending transmit command when the
COM20020ID next receives the tok en. Normall y, in an act ive net work, this command will set the TA status
bit to a logic "1" when the token is receiv ed. If the "Disable Transmitter" comman d does not cause the TA
bit to be set in the time it takes the token to make a round trip throu gh the network, one of three situati ons
exists. Either the node is disconnected from the network, or there are no other nodes on the network, or
the external receive circuitr y has failed. These situations can be determined by either u sing the improved
diagnostic features of the COM20020ID or using another soft ware timeout which is gr eater than the worst
case time for a round trip token pass, which occurs when all nodes transmit a maximum length message.
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6.4.3 Receive Sequence
A receive sequence begins with the RI status bit becoming a logic "1", which indicates that a previous
reception has concluded. The microcontroller will be interrupted if the corresponding bit in the Interrupt
Mask Register is set to logic "1". Otherwise, the microcontroller must periodically check the Status
Register. Once the microco ntroller is alerted to the fact that the previo us reception has concluded, it may
issue the "Enable Receive to Page fnn" command, which resets the RI bit to logic "0" and selects a new
page in the RAM buffer. Again, the appropriate buffer size is specified in the "Define Configuration"
command. Typically, the page which just received the data packet will be read by the microcontroller at
this point. Once the "Enable Receive to Page fnn" command is issued, th e microcontroller attends to oth er
duties. There i s no way of kn owing how long the n ew reception will take, since another nod e m ay tran smit
a packet at any time. When another node does transmit a packet to this node, and if the "Define
Configuration" command has enabled the reception of long packets, the COM20020ID interprets the
packet as either a long or short packet, depending on whether the content of the buffer location 2 is zero or
non-zero. The format of the buffer is shown in Figure 6.3. Address 0 c ontains the Source Identifier (SI D),
Address 1 contains the Destination Identifier (DID), and Address 2 contains, for short packets, the value
256-N, where N repr esents t he mess ag e le ngth, or for lon g pack ets, the valu e 0, indic ating th at it is ind eed
a long packet. In the latter case, Address 3 contains the value 512-N, where N represents the message
length. Note that on reception, the COM2 0020ID deposits packets into the RAM buffer in the same for mat
that the transmitting node arranges them, which allows for a message to be received and then
retransmitted without rearranging any bytes in the RAM buffer other than the SID and DID. Once the
packet is received and stored correctl y in the selected buffer, the COM20020ID sets the RI bit to logic "1"
to signal the microcontroller that the receptio n is complete.
Figure 6. 3 – Command Chaining Status Register Queue
TRI RI TA POR TEST RECON
TMA TTA
TMA TTA
TRI
MSB LSB
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6.5 Command Chaining
The Command Chain ing operation allows consecutiv e transmissions and recepti ons to occur without host
microcontroller intervention.
Through the use of a dual t wo-level FI FO, commands to be transmitted and received, as well as the status
bits, are pipelined.
In order for the COM20020ID to be compatible with previous SMSC ARCNET device drivers, the device
defaults to the non-chaining mode. In order to take advantage of the Command Chaining operation, the
Command Chaining Mode must be ena bled via a logic "1" on bit 6 of the Configuration Register.
In Command Chaining, the Status Register appears as in Figure 6.3.
The following is a list of Com mand Chaini ng guidelines for the software pr ogrammer. Further detail can be
found in the Transmit Command Ch aining and Receive Command Chaining sections.
The device is designed such that the interrupt service routine latency does not affect performance.
Up to two outstanding transmissions and two outstanding receptions can be pending at any given
time. The commands may be given in any order.
Up to two outstanding transmit interrupts and two outstanding receive interrupts are stored by the
device, along with their respective status bits.
The Interrupt Mask bits act on TTA (Rising Transition on Tr ansmitter Available) for transmit operations
and TRI (Rising Tr ansition of Receiver Inhibited) for receive operations. TTA is set upon completion
of a packet transmission only. TRI is set upon compl etion of a packet reception only. Typically ther e is
no need to mask the TTA and TRI bits after clearing the i nterrupt.
The traditional T A and RI bits are still av ailable to reflect the present status of the device.
6.5.1 Transmit Command Chaining
When the processor iss ues the first "Enable Transmit to Page fnn" command, the COM2 0020ID responds
in the usual manner by resetting the TA and TMA bits to prepare for the transmission from the specified
page. The TA bit can be used to see if there is currently a transmission pending, but the TA bit is really
meant to be used in the non-chaining mode only. The TTA bits provide the relevant information for the
device in the Command Chaining mode.
In the Command Chaining Mode, at any tim e after the first command is issued, the proc essor can issue a
second "Enable Transmit from Page fnn" command. The COM20020ID stores the fact that the second
transmit command was issued, along with the page number.
After the first transmission is completed, the COM20020I D updates the Status Register by setting the TT A
bit, which generates an interrupt. The interrupt service routine should read the Status Register. At this
point, the TTA bit will be foun d to be a logic "1" and the T MA (Transmit Message Acknowledge) bit will tell
the processor whether the transmission was successful. After reading the Status Register, the "Clear
Transmit Interrupt" command is issued, thus resetting the TTA bit and clearing the interrupt. Note that
only the "Clear Transmit Interrupt" command will clear the TTA bit and the interrupt. It is not necessary,
however, to clear the bit or the interrupt right away because the status of the transmit operati on is double
buffered in order to retain the results of the first transmission for analysis by the processor. This
information will remain in the Status Register until the "Clear Transmit Interrupt" command is issued. Note
that the interrupt will remain active until the command is issued, and the second interrupt will not occur
until the first interrupt is acknowledged. The COM20020ID guarantees a minimum of 200nS (at EF=1)
interrupt inactive time interval between interrupts. The TMA bit is also double buffered to reflect whether
the appropriate transmission was a success. The TMA bit should only be considered valid after the
corresponding TTA bit has been set to a logic "1". The TMA bit never causes an interrupt.
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When the token is received again, the second transmission will be automatically initiated after the first is
completed by using the stored "Enable Transmit from Page fnn" command. The operation is as if a new
"Enable Transmit from Page fnn" command has just been issued. After the first Transmit status bits are
cleared, the Status Register will again be updated with the results of the second transmission and a
second interrupt resulting from the second transmission will occur. The COM20020ID guarantees a
minimum of 200ns (at EF=1) interrupt inactive time interva l before the fo llowing edge.
The Transmitter Available (TA) bit of the Interrupt Mask Register no w masks only the TTA bit of the Status
Register, not the TA bit as in the non-c haining mode. Since the TT A bit is only set upon transmission of a
packet (not by RESET), and since the TTA bit ma y e asily be reset by issuing a "Clear T ransmit Interrupt"
command, there is no need to use the TA bit of the Interrupt Mask Register to mask interrupts generated
by the TTA bit of the Status Register.
In Command Chainin g mode, the "Disab le T ransmitter" c om mand will cancel the ol dest transmissi on. T his
permits canceling a packet destined for a no de not ready to receive. If both packets should be canceled,
two "Disable Transmitter" commands sh ould be issued.
6.5.2 Receive Command Chaining
Like the Transmit Command Chaining operation, the processor can issue two consecutive "Enable
Receive from Page fnn" commands.
After the first packet is received into the first specified page , the T RI bit of the Status Register will be set to
logic "1", causing an interrupt. Again, the interrupt need not be serviced immediately. Typically, the
interrupt service routine will read the Status Regist er. At this point, the RI bit will be foun d to be a lo gic "1".
After reading the Status Register, the "Clear Receiv e Interrupt" command should be issued, thus resetting
the TRI bit and clearing the interrupt. Note that onl y the "Clear Receive Interrupt" command will clear the
TRI bit and the interrupt. It is not necessary, ho wever, to clear the bit or the interrupt right a way because
the status of the receive oper ation is double buffered in order to retain the results of the first reception for
analysis by the processor, therefore the information will remain in the Status Register until the "Clear
Receive Interrupt" command is issued. Note that the interrupt will remain active until the "Clear Receive
Interrupt" command is issued, and the second interrupt will be stored until the first interrupt is
acknowledged. A minimum of 200nS (at EF=1) interrupt inactive time interval between interrupts is
guaranteed.
The second reception will occur as soon as a second packet is sent to the node, as long as the second
"Enable Receive to Page fnn" command was issued. The operation is as if a new "Enable Receive to
Page fnn" command has just been issued. After the first Receive status bits are cleared, the Status
Register will again be updated with the results of the second reception and a second interrupt resulting
from the second reception will occur.
In the COM20020ID, the Receive Inhibit (RI) bit of the Inter rupt Mask Register now masks only th e TRI bit
of the Status Register, not the RI bit as in the non-chaining mode. Since the TRI bit is only set upon
reception of a packet (not by RESET), and since the TRI bit may easily be reset by issuing a "Clear
Receive Interrupt" command, there is no need to use the RI bit of the Interrupt Mask Register to mask
interrupts generated by the TRI bit of the Status Register. In Command Chaining mode, the "Disable
Receiver" command will cancel the oldest reception, unless the reception has already begun. If both
receptions should be canceled, two "Disable Receiver" commands sh ould be issued.
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6.6 Reset Details
6.6.1 Internal Reset Logic
The COM20020ID includes special reset circuitry to guarantee smooth o peration during reset. Special care
is taken to assure proper operation in a variety of systems and modes of operation. The COM20020ID
contains digital filter circuitry and a Schmitt Trigger on the nRESET signal to reject glitches in order to
ensure fault-free operation.
The COM20020ID supports t wo reset options; software and hardware reset. A software reset is generated
when a logic "1" is written to bit 7 of the Configuration Register. The device remains in reset as long as
this bit is set. The software reset does not affect the microcontroller interface modes determined after
hardware reset, nor does it affect the contents of the Address Pointer Registers, the Configuration
Register, or the Setup1 Register. A hardware reset occurs when a low signal is asserted on the nRESET
input. The minimum reset pu lse width is 5T XTL. This pulse width is used by the internal digital filter, which
filters short glitches to allow only valid resets to occur.
Upon reset, the transmitter portion of the device is disab led and the inter nal registers assume thos e states
outlined in the Internal Registers section. After the nRESET signal is removed the user may write to the
internal registers. Since writing a non-zero value to the Node ID Register wakes up the COM20020ID
core, the Setup1 Register should be written before the Node ID Register. Once the Node ID Register is
written to, the COM20020ID reads the value and executes two write cycles to the RAM buffer. Address 0 is
written with the data D1H and address 1 is written with the Node ID. The data pattern D1H was chosen
arbitrarily, and is meant to provide assurance of proper microsequencer operation.
6.7 Initialization Sequence
6.7.1 Bus Determination
Writing to and reading from an odd address location from the COM20020ID's address space causes the
COM20020ID to determine the appropriate bus interface. When the COM20020ID is powered on the
internal registers may be written to. Since writing a non-zero value to the Node ID Register wakes up the
core, the Setup1 Register should be written to before the Node ID Register. Until a non-zero value is
placed into the NID Register, no microcode is executed, no tokens are passed by this node, and no
reconfigurations are generated by this node. Once a non-zero value is placed in the register, the core
wakes up, but the node will not attempt to join the network until the TX Enable bit of the Configuration
Register is set.
Before setting the TX Enable bit, the software may make some determinations. The software may first
observe the Receive Activity and the Token Seen bits of the Diag nostic Stat us Register to verif y the health
of the receiver and the net work.
Next, the uniqueness of the Nod e ID value placed in the Node ID Regis ter is determined. The TX Enabl e
bit should still be a logic "0" until it is ensured that the Node ID is unique. If this node ID already exists, the
Duplicate ID bit of the Diagnostic Status Register is set after a maximum of 420mS (or 840mS if the ET1
and ET2 bits are other than 1,1). To determine if another node on the network already has this ID, the
COM20020ID compares the value in the Node ID Register with the DID's of the token, and determines
whether there is a response to it. Once the Diagnostic Status Register is read, the DUPID bit is cleared.
The user may then attempt a new ID value, wait 420mS before checking the Duplicate ID bit, and repeat
the process until a unique No de ID is found. At this point, the T X Enable bit may be set to allow the no de
to join the network. Once the node joins the network, a reconfiguration occurs, as usual, thus setting the
MYRECON bit of the Diagnostic Status Register.
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The Tentative ID Register may be used to build a net work map of all the nod es on the net work, even once
the COM20020ID has joined the network. Once a value is placed in the Tentative ID Register, the
COM20020ID looks for a response to a token whose DID matches the Tentative ID Register. The
software can record this inform ation and continue placing T entative ID values into the register to continue
building the net work map. A complete network map is only valid until nodes are added to or deleted from
the network. Note that a node cannot detect the existence of the next logical node on the network when
using the Tentative ID. To determine the next logical node, the software should read the Next ID Register.
6.8 Improved Diagnostics
The COM20020ID allows the user to better manage the operation of the network through the use of the
internal Diagnostic Status Register.
A high level on the My Reconfiguration (MYRECON) bit indicates that the Token Reception Timer of this
node expired, causing a r econfigurati on by this node. After the Reconfig uration (RECON) bit of the Status
Register interrupts the microcontrol ler, the interrupt service routine will t ypically read the MYRECON bit of
the Diagnostic Status Register. Reading the Diagnostic Status Register resets the MYRECON bit.
Successive occurrences of a logic "1" on the MYRECON bit indic ates that a prob lem exists with this node.
At that point, the transmitter should be disabled so that the entire net work is not held do wn while the nod e
is being evaluated.
The Duplicate ID (DUPID) bit is used before the node joins the network to ensure that another node with
the same ID does not exist on the network. Once it is determined that the ID in the Node ID Register is
unique, the software should write a logic "1" to bit 5 of the Configuration Register to enable the basic
transmit function. This allows the node to join the network.
The Receive Activity (RCVACT) bit of the Diagnostic Status Register will be set to a logic "1" whenever
activity (logic "1") is detected on the RXIN pin.
The Token Seen (TOKEN) bit is set to a logic "1" whenever any token has been seen on the network
(except those tokens transmitted by this node).
The RCVACT and TOKEN bits may help the user to troubleshoot the network or the node. If unusual
events are occurring o n the net work, the user ma y find it valuab le to use th e TXEN bit of t he Configuratio n
Register to qualify events. Different combinations of the RCVACT, TOKEN, and TXEN bits, as shown
indicate different situations:
6.8.1 Normal Results:
RCVACT=1, TOKEN=1, TXEN=0: The nod e is not part of the net work. The network is operating pr operly
without this node.
RCVACT=1, TOKEN=1, TXEN=1: The node sees rece ive activity and sees the token. T he basic transmit
function is enabled. Network and node are operating properly.
MYRECON=0, DUPID=0, RCVACT=1, TXEN=0, TOKEN=1: Single node net work.
6.8.2 Abnormal Results:
RCVACT=1, TOKEN=0, TXEN=X: The nod e sees receive activity, but does not see the token. Either no
other nodes exist on the network, some type of data corruption exists, the media driver is malfunctioning,
the topology is set up incorrectly, there is noise on the network, or a reconf iguration is occurring.
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
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DATASHEET
RCVACT=0, TOKEN=0, TXEN=1: No receive activity is seen and the basic transmit function is enabled.
The transmitter and/or receiver are not functioning properly.
RCVACT=0, TOKEN=0, TXEN=0: No receive activity and basic transmit function disabled. This node is
not connected to the net work.
The Excessive NAK (EXCNAK) bit is used to replace a timeout function traditionally implemented in
software. This function is necessary to limit the num ber of times a sender issues a FBE to a no de with no
available buffer. When the destination node replies to 128 FBEs with 128 NAKs or 4 FBEs with 4 NAKs,
the EXCNAK bit of the sender is set, generating an interrupt. At this po int the software may abandon th e
transmission via the "Disable T ransmitter" command. This sets the TA bit to logic "1" when the node next
receives the token, to all ow a different transmission to occur. T he timeout value for the EXNACK bit (128
or 4) is determined by the FOUR-NAKS bit on the Setup1 Register.
The user may choose to wait for more NAK's before disabling the transmitter by taking advantage of the
wraparound counter of the EXCNAK bit. When the E XCNAK bit goes high, indicating 128 or 4 NAKs, the
"POR Clear Flags" command maybe issued to reset the bit so that it will go high again after another co unt
of 128 or 4. The software may count the number of times the EXCNAK bit goes high, and once the final
count is reached, the "Disable Transmitter" command may be issued.
The New Next ID bit permits the software to detect the withdrawal or addition of nodes to the network.
The Tentative ID bit allo ws the user to build a network map of those nodes existing on the network. This
feature is useful because it minimizes the need for human intervention. When a value placed in the
Tentative ID Register matches the Node ID of another node on the net wo rk, the TENTID bit is set, telling
the software that this NODE ID already exists on the network. The software should periodically place
values in the Tentative ID Register and monitor the New Next ID bit to maintain an updated net work map.
6.9 Oscillator
The COM20020ID contains c ircuitry which, in conjunctio n with an external paral lel resonant crystal or TT L
clock, forms an oscillator.
If an external cr ystal is used, two capac itors are needed (one from each leg of the crystal to ground). No
external resistor is required, since the COM20020ID contains an internal resistor. The crystal must have
an accuracy of 0.020% or better. The oscillation frequency range is from 10 MHz to 20 MHz.
The crystal must have an accurac y of 0.010 % or b etter when the inter nal clock multipl ier is turned o n. T he
oscillation frequency must be 20MHz when the internal clock multiplier is turned on.
The XTAL2 side of the crystal may be loaded with a single 74HC-type buffer in order to generate a clock
for other devices.
The user may attach an external TTL clock, rather than a crystal, to the XTAL1 signal. In this case, a
390Ω pull-up resistor is required on XTAL1, while XTAL2 should be left unconnected.
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
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Chapter 7 Operational Description
7.1 Maximum Guaranteed Ratings*
Operating Temperature Range..................................................................................................0oC to +70oC
Storage Temperature Range ................................................................................................-55oC to +150oC
Lead Temperature (soldering, 10 seconds) .......................................................................................+325 oC
Positive Voltage on any pin, with respect to ground ........................................................................VDD+0.3V
Negative Voltage on any pin, with respect to ground............................................................................. -0.3V
Maximum VDD ..........................................................................................................................................+7V
* Stresses above those listed may caus e permanent damage to the dev ice. This is a stress rating only and
functional operation of the device at these or any other co ndition above those indicated in the operational
sections of this specification is not implied.
Note: When powering this device from laboratory or system power supplies, it is important that the Absolute
Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage
spikes or "glitches" on their outputs when the AC power is switched on or off. In addition, voltage
transients on the AC po wer line may a ppear on t he DC outpu t. If this possibility exists it is suggested that
a clamp circuit be used.
7.2 DC Electrical Characteristics
VDD=5.0V±10%
COM20020: TA=0oC to +70oC, COM20020I: TA=-40oC to +85oC
PARAMETER SYMBOL MIN TYP MAX UNIT COMMENT
Low Input Voltage 1
(All inputs except A2,
XTAL1, nRESET, nRD,
nWR, and RXIN)
High Input Voltage 1
(All inputs except A2,
XTAL1, nRESET, nRD,
nWR, and RXIN)
VIL1
VIH1
2.0
0.8 V
V
TTL Levels
TTL Levels
Low Input Voltage 2
(XTAL1)
High Input Voltage 2
(XTAL1)
VIL2
VIH2
4.0
1.0 V
V
TTL Clock Input
Low to High Threshold
Input Voltage
(A2, nRESET, nRD, nWR, and
RXIN)
High to Low Threshold
Input Voltage
(A2, nRESET, nRD, nWR, and
RXIN)
VILH
VIHL
1.8
1.2
V
V
Schmitt Trigger,
All Values at VDD =
5V
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
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PARAMETER SYMBOL MIN TYP MAX UNIT COMMENT
Low Output Voltage 1
(nPULSE1 in Push/Pull
Mode, nPULSE2,
NTXEN)
High Output Voltage 1
(nPULSE1 in Push/Pull
Mode, nPULSE2,
nTXEN)
VOL1
VOH1
VOH1C
2.4
0.8 x VDD
0.4
V
V
ISINK=4mA
ISOURCE=-2mA
ISOURCE=-200µA
Low Output Voltage 2
(D0-D7)
High Output Voltage 2
(D0-D7)
VOL2
VOH2
2.4
0.4 V
V
ISINK=16mA
ISOURCE=-12mA
Low Output Voltage 3
(nINTR)
High Output Voltage 3
(nINTR)
VOL3
VOH3
2.4
0.8 V
V
ISINK=24mA
ISOURCE=-10mA
Low Output Voltage 4
(nPULSE1 in Open-Drain
Mode)
VOL4 0.5 V ISINK=48mA
Open Drain Driver
Dynamic VDD Supply
Current IDD
40 mA
5 Mbps
All Outputs Open
Input Pull-up Current
(nPULSE1 in Open-Drain
Mode, A1, AD0-AD2,
D3-D7)
Input Leakage Current
(All inputs except A1,
AD0-AD2, D3-D7,
XTAL1, XTAL2
IP
IL
80 200
±10
μA
μA
VIN=0.0V
VSS < VIN < VDD
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
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CAPACITANCE (TA = 25°C; fC = 1MHz; VDD = 0V)
Output and I/O pins capacitive load specified as follows:
PARAMETER SYMBOL MIN TYP MAX UNIT COMMENT
Input Capacitance CIN 5.0 pF
Output Capacitance 1
(All outputs except XTAL2,
nPULSE1 in Push/Pull
Mode)
Output Capacitance 2
(nPULSE1, in BackPlane
Mode Only - Open
Drain)
COUT1
COUT2
45
400
pF
pF
Maximum Capacitive
Load which can be
supported by each
output.
0.4V
AC Measurements are taken at the following points:
Inputs:
2.4V
1.4V 50%
50%
0.4V
2.4V
1.4V
0.8V
Outputs:
2.0V
0.8V
2.0V
Inputs are driven at 2.4V for logic "1" and 0.4 V for logic "0" except XTAL1 pin.
Outputs are measured at 2.0V min. for logic "1" and 0.8V max. for logic "0".
t
t
t
t
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Datasheet
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Chapter 8 Timing Diagrams
Figure 8.1 – Multiplexed Bus, 68XX-Like Control Signals; Read Cycle
A
D0-AD2, VALID
nCS t1
t3
t8
ALE
VALID DATA
t2,
t6
t5
t4
t7
D3-D7
DIR t9 t10
nDS
t11
t12
t13 t14
Note 2
Parameter min max units
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
Address Setup to ALE Low
Address Hold from ALE Low
nCS Setup to ALE Low
nCS Hold from ALE Low
ALE Low to nDS Low
nDS Low to Valid Data
nDS High to Data Hig h Impedance
Cycle Ti me (nDS Low to Next Tim e Lo w)
DIR Setup to nDS Active
DIR Hold from nDS Inactive
ALE High Width
ALE Low Width
nDS Low Width
nDS High Width
20
10
10
10
15
0
4TARB*
10
10
20
20
60
20
40
20
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
MUST BE: RBUSTMG bit = 0
TARB is the Arbitration Clock Period
TARB is identical to Topr if SLOW ARB = 0
*
TARB is twice Topr if SLOW ARB = 1
The Microcontroller typ ical ly acce sses the COM200 20 on every other cycl e.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20020 cycles.
Note 1:
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
Note 2: Read cycle for Address Pointer Low/High Registers occurring after an access
to Data Register re quires a minimum of 5TARB from the trail ing edge of nDS to
the leading ed ge of the next nDS.
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Datasheet
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DATASHEET
Figure 8.2 – Multiplexed Bus, 80XX-Like Control Signals; Read Cycle
A
D0-AD2, VALID
nCS
t1
t3
t8
ALE
VALID DATA
t2,
t6
t5
t4
t7
D3-D7
nRD t9
t10
nWR t13 t11 t12
Note 3
Note 2
ALE High Width
ALE Low Width
nRD Low Width
nRD High Width
nWR to nRD Lo w
Parameter min max units
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
Address Setup to ALE Low
Address Hold from ALE Low
nCS Setup to ALE Low
nCS Hold from ALE Low
ALE Low to nRD Low
nRD Low to Valid Data
nRD High to Data High Impedance
Cycle Time (nRD Low to Ne xt Tim e Low)
20
10
10
10
15
0
4TARB*
40
20
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
MUST BE: RBUSTMG bit = 0
20
20
60
20
20
The Microcontroller typically accesses the COM20020 on every other cycle.
Theref ore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20020 cycles.
Note 1:
TARB is the Arbitration Clock Period
TARB is identical to Topr if SLO W ARB = 0
*
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
Note 2: Read cycle fo r Address Pointe r Low/High Registers occurring after a read from
Data Register requires a minimum of 5TARB from the trailing edge of nRD to the
leading edge of the next nRD.
Note 3: Read cycle fo r Address Pointe r Low/High Registers occurring after a write to
Data Register requires a minimum of 5TARB from the tr ailing edge of nWR to the
leading edge of nRD.
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Datasheet
SMSC COM20020I Rev D Page 55 Revision 12-05-06
DATASHEET
Figure 8.3 - Multiplexed Bus, 68XX-L i ke Control Signals; Write Cycle
A
D0-AD2, VALID
nCS t1
t3
t8
ALE
VALID DATA
t2,
t6
t5
t4
t7
D3-D7
DIR
t9 t10
Note 2
t8**
nDS
t11
t12
t13 t14
Parameter min max units
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
20
10
10
10
15
10
4TARB*
10
10
20
20
20
20
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
Address Setup to ALE Low
Address Hold from ALE Low
nCS Setup to ALE Low
nCS Hold from ALE Low
ALE Low to nDS Low
Valid Data Setup to nDS High
Data Hold from nDS High
DIR Setup to nDS Active
DIR Hold from nDS Inactive
30
ALE High Width
ALE Low Width
nDS Low Width
nDS High Width
Cycle Time (nDS to Next )**
The Microcontroller typically accesses the COM20020 on every other cycle.
Theref o re, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20020 cycles.
Note 1:
An y cycle occurring after a write to Ad dres s Poi n t er Low Register r e quires a
minimum of 4TARB from the trailing edge of nDS to the leading edge of the
next nDS.
Note 2:
**
TARB is the Arbitration Clock Period
TARB is identical to Topr if SLOW ARB = 0
*
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
Write cycle for Address P ointer Low Register occurring after an access to
Data Register requires a minimum of 5TARB from the trailing edge of nDS to
the leading edge o f the next nDS.
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Datasheet
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DATASHEET
Figure 8.4 - Multiplexed Bus, 80XX-L i ke Control Signals; Write Cycle
A
D0-AD2, VALID
nCS t1
t3
ALE
VALID DA TA
t2,
t6
t5
t4
t7
D3-D7
Note 2
t8**
nWR
t9
t10
nRD t13 t11 t12 t8
Note 3
Parameter min max units
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
20
10
10
10
15
10
4TARB*
20
20
20
20
20
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
Address Setup to ALE Low
Address Hold from ALE Low
nCS Setup to ALE Low
nCS Hold from ALE Low
ALE Low to nDS Low
Valid Data Setup to nDS High
Data Hold from nDS High 30
ALE High Widt h
ALE Low Wid th
nWR Low Width
nWR High Wid th
nRD to nWR Low
Cycle Time (nWR to Next )**
TARB is the Arbitration Clock P eriod
TARB is identical to Topr if SLOW ARB = 0
*
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
The Microcontroller typically accesses the COM20020 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20020 cycles.
Note 1:
Any cycle occurring after a write to Address Pointer Low Register requires a
minimum of 4TARB from the trailing edge of nWR to the leading edge of the
next nWR.
Note 2:
**
Write cycle for Address Pointer Low Register occurring after a write to Data
Register requires a mini mum of 5TARB from the trailing edge of nWR to the
leading edge of the next nWR.
Note 3: Write cycle for Address Pointer Low Register occurring after a read from Data
Register requires a minimum of 5TARB from the tr a ili ng ed ge of nRD to the
leading edge of nWR.
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Datasheet
SMSC COM20020I Rev D Page 57 Revision 12-05-06
DATASHEET
Figure 8.5 - Non-Multiplexed Bus, 80XX-L i ke Control Signals; Read Cycle
A
0-A2
VALID DATA
VALID
D0-D7
nCS
t6
t1
t7
t3 t5
t4
t2
nRD
nWR
t10 t8 t9
Note 3
Note 2
Parameter min max units
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
15
10
5**
0
nS
nS
nS
nS
Address Setup to nRD Active
Address Hold from nRD Inactive
nCS Setup to nRD Active
nCS Hold from nRD Inactive
Cycle Time (nRD Low to Next Time Low)
nRD Low to Valid Data
nRD High to Data High Impedance
4TARB*
0
60
20
20
40**
20
nS
nS
nS
nS
nS
nS
CASE 1: RBUSTMG bit = 0
nRD Low Width
nRD High Width
nWR to nRD Low
TARB is the Arbitration Clock Period
TARB is identical to Topr if SL OW ARB = 0
*
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
nCS may become activ e after contro l becomes active, b u t the access time (t6)
will now be 45nS measured from the leading edge of nCS.
**
The Microcontroller typically accesses the COM20020 on ev ery other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20020 cycles.
Note 1:
Note 2: Read cycle for Address Pointer Low/High Registers occurring after a read from
Data Register requires a minimum of 5TARB from the trailing edge of nRD to the
leading edge of the next nRD.
Note 3: Read cycle for Address Pointer Low/High Registers occurring after a write to
Data Register requires a minimum of 5TARB from the trailing edge of nWR to the
leading edge of nRD.
**
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
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Figure 8.6 - Non-Multiplexed Bus, 80XX-L ike Control Signals; Read Cycle
A
0-A2
VALID DATA
VALID
D0-D7
nCS
t6
t1
t7
t3 t5
t4
t2
nRD
nWR
t10 t8 t9
Note 3
Note 2
Parameter min max units
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
-5
0
-5
0
nS
nS
nS
nS
Address Setup to nRD Active
Address Hold from nRD Inactive
nCS Setup to nRD Activ e
nCS Hold from nRD Inactive
Cycle Time (nRD Low to Next Time Low)
nRD Low to Valid Data
nRD High to Data Hi gh Impedance
4TARB*+30
0
100
30
20
60**
20
nS
nS
nS
nS
nS
nS
nRD Low Width
nRD High Width
nWR to nRD Low
CASE 2: RBUSTMG bit = 1
The Microcontroller typically accesses the COM20020 on e v ery other cycle.
Therefore, the cycle time specif ied in the microcontroll er's datasheet
should be doubled when considering back-to-back COM20020 cycles.
Not e 1:
t6 is measured from the latest active (valid) timing among nCS, nRD , A0-A2.**
TARB is the Arbitration Clock Period
TARB is identical to Topr if SLOW ARB = 0
*
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
Not e 2: Read cycle for Address Pointer Low/High Registers occurring after a read from
Data Register requires a minimum of 5TARB from the trailing edge of nRD to the
leading edge of the next nRD.
Not e 3: Read cycle for Address Pointer Low/High Registers occurring after a write to
Data Register requires a minimum of 5TARB from the trailing edge o f nWR to the
leading edge of nRD.
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Datasheet
SMSC COM20020I Rev D Page 59 Revision 12-05-06
DATASHEET
Figure 8.7 - Non-Multiplexed Bus, 68XX-L ike Control Signals; Read Cycle
A0-A2
VALID DA TA
VALID
D0-D7
nCS
t8
t1
t9
t3
t6
t4
t2
nDS
DIR t5 t7
t10 t11
Note 2
Parameter min max units
t1
t2
t3
t4
t5
t6
t7
15
10
5**
0
nS
Address Setup to nDS Active
Address Hold from nDS Inactive
nCS Setup to nDS Active
nCS Hold from nDS Inactive
DIR Setup to nDS Active
Cycle Time (nDS Low to Next Time Low)
DIR Hold from nDS Inactive 4TARB*
nS
nS
nS
nS
nS
nS
t8 nS
nDS Low to Valid Data 40**
t9
t10
t11
nS
nS
nS
nDS High to Data High Impedence
nDS Low Width
nDS High Width
20
10
10
0
60
20
CASE 1: RBUSTMG bit = 0
The Microcontroller typically accesses the COM20020 on e very other cycle.
Therefore, t he cycle t ime spe cified in the m icrocontr oller's datasheet
should be doubled when considering back-to-back COM20020 cycles.
Note 1:
nCS may become active after control becomes active, but th e access time (t8) will
now be 45nS me asured from the leading edge of nCS.
**
TARB is the Arbitration Clock Period
TARB is identical to Topr if SLOW ARB = 0
*
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
Note 2: Read cycle for Ad dress Pointer Low/High Registe rs occurring after an access
to Data Register requires a minimum of 5TARB from the trailing edge of nDS to
the leading edge of the next nDS.
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Datasheet
Revision 12-05-06 Page 60 SMSC COM20020I Rev D
DATASHEET
Figure 8.8 - Non-Multiplexed Bus, 68XX-L ike Control Signals; Read Cycle
A0-A2
VALID DATA
VALID
D0-D7
nCS
t8
t1
t9
t3
t6
t4
t2
nDS
DIR t5 t7
t10 t11
Note 2
Parameter min max units
t1
t2
t3
t4
t5
t6
t7
-5
0
-5
0
nS
Address Setup to nDS Active
Address Hold from nDS Inactive
nCS Setup to nDS Active
nCS Hold from nDS Inactive
DIR Setup to nDS Active
Cycle Time (nDS Low to Next Time Low)
DIR Hold from n DS I na ctive 4TARB*+30
nS
nS
nS
nS
nS
nS
t8 nSnDS Lo w to Valid Da t a 60**
t9
t10
t11
nS
nS
nS
nDS High to Data High Impedence
nDS Lo w Wi d t h
nDS High Width
20
10
10
0
100
30
CASE 2: RBUSTMG bit = 1
The Microcontroller typically accesses the COM20020 on every other cycle.
Therefore, the cycle time specified in th e microco n troller's datashe et
should be doubled when considering back-to-back COM20020 cycles.
Note 1:
** t8 is measured from the latest active (valid) timing among nCS , nDS, A0-A2 .
TARB is the Arbitration Clock Period
TARB is identical to Topr if SLOW ARB = 0
*
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
Note 2: Read cycle for Address Pointer Low/High Registers occurring after an access
to Data Register requires a minimum of 5TARB from the trailing edge of nDS to
the leading edge of the next nDS.
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Datasheet
SMSC COM20020I Rev D Page 61 Revision 12-05-06
DATASHEET
Data Hold from nWR High
nWR Low Width
nWR High Width
nRD to nWR Low
A0-A2
VALID DATA
VALID
D0-D7
nCS
t6
t1
t7
t3 t4
t2
Note 2
nWR
nRD t10 t8 t9 t5
Note 3
t5**
t1
t3
t5
t6
t7
t8
t9
t10
Parameter
Address Setup to n WR Active
nCS Setup to WR Active
Valid Data Setu p to nWR High
min
15
5
10
20
20
20
max
4TARB*
30***
units
nS
nS
nS
nS
nS
nS
nS
nS
t4 nCS Hold from nWR Inactive 0nS
t2 Address Hold from nWR Inactive 10 nS
Cycle Time (nWR to Next )**
***: nCS may become active after control becomes active, but the data setup time will now
be 30 nS measured from the later of nCS falling or V alid Data available.
The Microcontroller typically accesses the COM20020 on every other cycle.
There fore, the cycle tim e specifie d in th e microcontroll e r 's da tasheet
should be double d when considering back-to-back COM20020 cycles.
Note 1:
Note 2: Any cycle occurring a fter a write to the Address Pointer Low Register
requires a minimum of 4TARB from the trailing edge of nWR to the leading edge
of the next nWR.
TARB is the Arbitration Clock Period
TARB is identi cal to Topr if SLOW ARB = 0
*
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation cloc k. It depends on CKUP1 and CKUP0 bits
Write cycle for Address Pointer Low Register occurring aft er a write t o Data
Register requires a minimum of 5TARB from the trailing edge of nWR to the
leading edge of the next nWR.
Note 3: Write cycle for Address Point er Low Register occurring after a rea d from Data
Register requires a minimum of 5TARB from the trailing edge of nRD to th e
leading edge of nWR.
**
Figure 8.9 - Non-Multiplexed Bus, 80XX-L i ke Control Signals; Write Cycle
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Datasheet
Revision 12-05-06 Page 62 SMSC COM20020I Rev D
DATASHEET
A0-A2
VALID DATA
VALID
D0-D7
nCS
t8
t1
t9
t3
t10
t4
t2
Note 2
t5
DIR
t7
nDS t11
t6
t6**
Parameter min max units
Address Setup to nDS Active
Address Hold from nDS Inactive
nCS Setup to nDS Active
nCS Hold from nDS Inactive
DIR Setup to nDS Active
Cycle Time (nDS to Next Time )**
DIR Hold from nDS Inactive
Valid Data Se t up to nDS High
Data Hold from nDS High
nDS Low Width
nDS High Width
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
15
10
5
0
10
4TARB*
10
30***
10
20
20
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
***: nCS may become active after control becomes active, but the data setup time will now
be 30 nS measured from the later of nCS falling or Valid Data available.
TARB is the Arbitration Clock Period
TARB is identical to Topr if SLOW ARB = 0
*
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
The Microcontroller typical ly accesses the COM20020 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20020 cycles.
Note 1:
**Note 2: Any cycle occurring after a write to the Address Poi n t er Low Register
requires a m in i mum of 4TARB from the tra iling edge of nDS to the lead ing edge
of the next nDS.
Write cycle for Address Pointer Low Registers occurring aft er an access to
Data Register requires a minimum of 5TARB from the trailing edge of nDS to
the leading edge of the next nDS.
Figure 8.10 - Non-Multiplexed Bus, 68XX-Like Control Signals; Write Cycle
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Datasheet
SMSC COM20020I Rev D Page 63 Revision 12-05-06
DATASHEET
nPULSE2
t1
t3
t7
t8
Parameter
nPULSE1, nPULSE2 Pulse Width
nPULSE1, nPULSE2 Overlap
RXIN Perio d
RXIN Inactive Pulse Width
min
100
-10
max units
nS
nS
nPULSE1
t1
t6 RXIN Active Pulse Width
t2
t2 nPUL SE1, nP ULSE2 Period nS
t1
t3
400
0+10
typ
RXIN
t6
t7
10 400
nTXEN
nS
nS
t2
t4 t5
LAST BI T
(400 nS BIT TIME)
t4 nTXEN Low to nPULSE1 Low 850 950 nS
t5 Beginning of Last Bit Time to nTXEN High 250 350 nS
100
t8
20 nS
Note: Use Only 2.5 Mbps
Figure 8.11 - Normal Mode Transmit or Receive Timing
(These signals are to and from the h ybrid)
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Datasheet
Revision 12-05-06 Page 64 SMSC COM20020I Rev D
DATASHEET
nPULSE1 t2 t3
RXIN t10
t11
nPULSE2 t5 t6
(Internal Clk)
t4
Parameter min typ max units
t2
t3
t4
t5
t6
t7
t8
t10
t11
t12
nPULSE1 Pulse Width
nPULSE1 Period
nPULSE2 Low to nPULSE1 Low
nPULSE2 High Ti me
nPULSE2 Low Time
nPULSE2 Period
nPULSE2 High to nTXEN Hig h
RXIN Active Pulse Width
RXIN Period
nS
nS
nS
nS
nS
nS
nS
nS
nS
200*
400*
100*
100*
200*
200*
400*
50
50
-25
10
t1
t7
nTXEN
t9 t8
LAST BIT
(400 nS BIT TIME)
t1 nPULSE2 High to nTXEN Low -25 50 nS
(First Rising Edge on nPULSE2 after Last Bit Time)
t9 nTXEN Lo w to first nPULSE1 Low** 650 750 nS
t13
t12
-25
RXIN Inactive Pulse Width 20 nS
t13 Beginning Last Bit Time to nTXEN High** 450 nS
Above values are for 2.5 Mbps.
Other Data Rates are shown below.
550
TDR is the Data Rate Period
*t5, t6 = TDR/4
*t2, t7, t10 = TDR/2
*t3, t11 = TDR
**t9 = x TDR +/- 50 nS
7
4
**t13 = x TDR +/- 50 nS
5
4
Figure 8.12 - Backplane Mode Transmit or Receive Timing
(These signals are to and from the differential driver or the cable)
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Datasheet
SMSC COM20020I Rev D Page 65 Revision 12-05-06
DATASHEET
t1
t3
Parameter
Input Clock High Time
Input Clock Period
min
10
25
max units
nS
nS
XTAL1
t1
t4 Input Clock Frequency 100
t2 Input Clock Low Time nS
t3
10
typ
10
t2
40 MHz
t5 Frequency Accu racy* -200 200 ppm
Note*: Input clock frequency must be 20 MHz ( 100ppm or better) to use the internal Clock Multiplier .
+
-
t5is applied to crystal oscillaton.
4.0V 1.0V 50% of VDD
Figure 8.13 - TTL Input Timing on XTAL1 Pin
t1
Parameter
nRESET Pulse Width***
min max units
nRESET
t1
t2 nINTR High to Ne xt nINTR Low
typ
t2
nINTR
5TXTL*
EF = 0
EF = 1 TDR**/2
4TXTL*
Note*: TXTL is period of e xternal XTAL oscillation frequency.
Note **: TDR is period of Data Rate (i.e. at 2.5 Mbps, TDR = 400 nS)
Note***: When the power is turned on, t1 is measured from stable XTAL
oscillation after VDD was ov er 4.5V.
Figure 8.14 - Reset and Interrupt Timing
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Datasheet
Revision 12-05-06 Page 66 SMSC COM20020I Rev D
DATASHEET
Chapter 9 Package Outlines
Figure 9.1 - 28 Pin PLCC Packag e Dimensions
A
A1
B
B1
C
D
D1
D2
D3
E
F
G
R
.160-.180
.090-.120
.013-.021
.026-.032
.020-.045
.485-.495
.450-.456
.390-.430
.300 REF
.050 BSC
.042-.056
.042-.048
.025-.045
DIM 28L
J .000-.020
NOTES:
All dim ensio ns are in inches.
Circle in dicating pin 1 can appear on a top surface as shown on the drawing or
right above it on a beveled edge.
1.
2.
PIN NO.
1
GEJ
D3
JD1
D
J
B1
B
A
A1
C
D2
F
R
Base
Plane
Seating
Plane
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Datasheet
SMSC COM20020I Rev D Page 67 Revision 12-05-06
DATASHEET
Figure 9.2 - 48 Pin TQFP Package Outline
Table 9.1 - 48 Pin TQFP Package Parameters
MIN NOMINAL MAX REMARK
A ~ ~ 1.6 Overall Package Height
A1 0.05 0.10 0.15 Standoff
A2 1.35 1.40 1.45 Body Thickness
D 8.80 9.00 9.20 X Sp an
D/2 4.40 4.50 4.60 1/2 X Span Measure from Centerline
D1 6.90 7.00 7.10 X body Size
E 8.80 9.00 9.10 Y Span
E/2 4.40 4.50 4.60 1/2 Y Span Measure from Cent erline
E1 6.90 7.00 7.10 Y body Size
H 0.09 ~ 0.20 Lead Frame Thickness
L 0.45 0.60 0.75 Lead Foot Length from Centerline
L1 ~ 1.00 ~ Lead Length
e 0.50 Basic Lead Pitch
θ 0o ~ 7o Lead Foot Angle
W 0.17 ~ 0.27 Lead Width
R1 0.08 ~ ~ Lead Shoulder Radius
R2 0.08 ~ 0.20 Lead Foot Radius
ccc ~ ~ 0.0762 Coplanarity (Assemblers)
ccc ~ ~ 0.08 Coplanarity (Test House)
Note 1: Controlling Unit: millimeter
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Datasheet
Revision 12-05-06 Page 68 SMSC COM20020I Rev D
DATASHEET
Appendix A
This appendix describes the function of the NOSYNC and EF bits.
NOSYNC Bit
The NOSYNC bit controls whether or not the RAM initialization sequence requires the line to be idle by
enabling or disabling the SYNC command during initialization. It is defined as follows:
NOSYNC: Enable/Disable SYNC command during initialization. NOSYNC=0, Enable (Default): the line
has to be idle for the RAM initialization sequence to be written, NOSYNC=1, Disable: the line does not
have to be idle for the RAM initialization sequence to be written.
The following discussion describes the function of this bit:
During initialization, after the CPU writes the Node ID, the COM20020ID will write "D1"h data to Address
000h and Node-ID to Address 001h of its internal RAM within 6uS. These values are read as part of the
diagnostic test. If the D1 and Node-ID initialization sequence cannot be read, the initialization routine will
report it as a device diagnostic failure. These writes are controlled by a micro-program which sometimes
waits if the line is active; SYNC is the micro-program command that causes the wait. When the micro-
program waits, the initial RAM write does not occur, which causes the d iagnostic error. Thus in th is case,
if the line is not idle, the initialization sequence may not be written, which will be reported as a device
diagnostic failure.
However, the initialization sequence and diagnostics of the COM20020ID should be independent of the
network status. This is accomplished through some additional logic to decode the program counter,
enabled by the NOSYNC bit. When it finds that the micro-program is in th e initialization r outin e, it disables
the SYNC command. In this case, the initialization will not be held up b y the li ne status.
Thus, by setting the NOSYNC bit, the line does not have to be idle for the RAM initialization sequence to
be written.
EF Bit
The EF bit controls several modifications to internal operation timing and logic. It is defined as follo ws:
EF: Enable/Disable the new internal operation timing and logic refinements. EF=0: (Default) Disable the
new internal operation timing (the timing is the same as in the COM20020 Rev. B); EF=1: Enable the ne w
internal operation timing.
The EF bit controls the following timing/logic refinements in the COM20020ID:
a) Extend Interrupt Disable Time
While the interrupt is active (nINTR pin=0), the interrupt is disabled b y writing the Cle ar Tx/R x interr upt an d
Clear Flag command and by reading the Next-ID register. This minimum disable time is changed by the
Data Rate. For example, it is 200 nS at 2.5 Mbps and 100 nS at 5 Mbps. The 100 nS width will be too
short to for the Interrupt to be seen.
Setting the EF bit will change the minimum disable time to always be more than 200 nS even if the Data
Rate is 5 Mbps . This is done by changing the clock which is supplied to the Interrupt Disable logic. The
frequency of this clock is always less than 20 MHz even if the data rate is 5 Mbps.
b) Synchronize the Pre-Scalar Output
The Pre-Scalar is used to change the data rate. The output clock is sel ected by CKP3-1 bits in the Set-Up
register. The CKP3-1 bits are changed by writing the Set-Up register from outside the CPU. It's not
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Datasheet
SMSC COM20020I Rev D Page 69 Revision 12-05-06
DATASHEET
synchronized between the CPU and COM20020ID. Thus, changing the CKP3-1 timing does not
synchronize with the internal clocks of Pre-Scalar, and changing CKP3-1 may cause spike noise to appear
on the output clock line.
Setting the EF bit will include flip-flops inserted between the Configuration register and Pre-Scalar for
synchronizing the CKP3-1 with Pre-Scalar’s internal clocks.
Never change the CKP3-1 when the data rate is over 5 Mbps. T he y must all be zero.
c) Shorten The Write Interval T ime To The Command Register
The COM20020ID limits the write interval time for continuous writing to the Command register. The
minimum interval time is chan ged by the Data Rate. It's 100 nS at the 2.5 Mbps and 1.6 μS at the 156.25
Kbps. This 1.6 μS is very long for CPU.
Setting the EF bit will change the clock so urce from OSCK clock (8 times frequency of data rate) to XTAL
clock which is not changed by the data rate, such that the minimum interval time becomes 100 nS.
d) Eliminate The Wr ite Prohibition Period For The Enable Tx/Rx Commands
The COM20020ID has a write prohibition period for writing the Enable Transmit/Rece ive Commands. This
period is started by the TA or RI bit (Status Reg.) returning to High. This prohibition period is caused by
setting the TA/RI bit with a pulse signal. It is 3.2 μS at 156.25 Kbps. T his period may be a problem whe n
using interrupt processing. The interru pt occurrs when the RI bit returns to High. The CPU writes the next
Enable Receive Command to the other page immediately. In this case, the interval time between the
interrupt and writing Command is shorter than 3.2 μS.
Setting the EF bit will cause the T A/RI bit to return to High upon releas e of the pulse signal for setting the
TA/RI bit, instead of at the start of the pulse. This is illustrated in Figure 0.1 on the following page.
The EF bit also controls the resolution of the following issues from the COM20020 Rev. B:
a) Network MAP Generation
Tentative ID is used for generating the Network MAP, but it sometimes detects a non-existent no de. Every
time the Tentative-ID register is written, the effect of the old T entative-ID remains active for a while, which
results in an incorrect network map. It can be avoided by a carefully coded software routine, but this
requires the programmer to have de ep knowledge of ho w the COM20020ID works. Duplicate-ID is mainl y
used for generating the Network MAP. This has the same issue as Tentative-ID.
A minor logic change clears all the remaining effects of the old Tentative-ID and the old Duplicate-ID, when
the COM20020ID detects a write operation to Tentative-ID or Node-ID register. With this change,
programmers can use the Tentative-ID or Duplicate-ID for generating the network MAP without any issues .
This change is Enabled/Disabled by the EF bit.
b) Mask Register Reset
The Mask register is reset by a soft reset in the COM20020 Rev. A, but is not reset in Rev. B. The Mask
register is related to the Status and Diagnostic register, so it should be reset by a soft reset. Otherwise,
every time the soft reset happens, the COM20020 Rev. B generates an unnecessary interrupt since the
status bits RI and TA are back to one by the soft reset.
This is resolved by changing the logic to reset the Mask register both by the hard reset and by the soft
reset. The soft reset is activated by the Node-ID register goin g to 00h or by the RESET bit going to Hi gh in
the Configuration register. This solution is Enabled/Disabled by the EF bit.
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Datasheet
Revision 12-05-06 Page 70 SMSC COM20020I Rev D
DATASHEET
Tx/Rx comp leted
TA/RI bit
Se tti n g P u lse
nINTR p in
prohibition period
EF=1 Tx/Rx com pleted
TA/RI bit
Settin g Pulse
nINTR pi n
EF=0
Figure 0.1 - Effect of the EF Bit on the T A/RI Bit
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Datasheet
SMSC COM20020I Rev D Page 71 Revision 12-05-06
DATASHEET
Appendix B - Example of Interface Circuit Diagram to
ISA Bus
ISA Bus
AEN
SA15-SA4
SD7-SD0
nIOR
nIOW
SA2-SA0
IRQm
nIOCS16
DRQn
nDACK
TC
nREFRESH
RESETDRV
12
12 bit
Comparators
LS688x2
nG
PP=Q QI/O Address Seeting (DIP Switches)
16 bit Bus
Transceivers
LS245
AB
DIR nG
3
D7-D0
nRD
nWR
A2-A0
nINTR
nRESET
nCS
8
3
Schmitt-Trigger Buffer
12 COM20020
8
A
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Datasheet
Revision 12-05-06 Page 72 SMSC COM20020I Rev D
DATASHEET
Appendix C - Software Identification of the
COM20020 Rev B, Rev C and Rev D
In order to properly write software to work with the COM20020 Rev B, C and D it is necessar y to be a bl e to
identify the different revisions of the part.
To identify the COM20020 Revision fo llow the following procedure:
1. Write 0x98 to Register-6 (Address = 6)
2. Write 0x02 to Register-5 (Address = 5)
3. Read Register-6
* If the value read from Register-6 is 0x98 then the part is a COM20020 Rev B or earlier
* If the value read from Register-6 is 0x9A then go to next step below
4. Write 0x80 to Register-5
5. Read Register-5
* If the value read from Register-5 is 0x00 then the part is a COM20020 Rev C
* If the value read from Register-5 is 0x80 then the part is a COM20020 Rev D
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