Am27H010 1 Megabit (131,072 x 8-Bit) High Speed CMOS EPROM al Advanced Micro Devices DISTINCTIVE CHARACTERISTICS Mm Fast access time 45ns m@ JEDEC-approved pinout Plug in upgrade of standard 1 Mbit EPROMs Easy upgrade from 28-pin JEDEC EPROMs HM Single +5 V power supply m@ +10% power supply tolerance available @ 100% Flashrite programming Typical programming time of 16 seconds @ Latch-up protected to 100 mA from 1 V to Vec+1V @ High noise immunity @ Compact 32-pin DIP, PDIP, LCC and PLCC packages @ DESC SMD No. 5962-89614 GENERAL DESCRIPTION The Am27H010 is a1 Mbit ultraviolet erasable program- mable read-only memory. It is organized as 131,072 words by 8 bits per word, operates froma single +5 V supply, has astatic standby mode, and features fast sin- gle address location programming. Products are avail- able in windowed ceramic DIP and LCC packages as well as plastic one time programmable (OTP) PDIP and PLCC packages. Typically, any byte can be accessed in less than 45 ns, allowing operation with high-performance microproces- sors without any WAIT states. The Am27H010 offers separate Output Enable (OE) and Chip Enable (CE) controls, thus eliminating bus contention in a multiple bus microprocessor system. AMDs CMOS process technology provides high speed, low power, and high noise immunity. Typical power con- sumption is only 220 mW in active mode, and 50 mW in standby mode. All signals are TTL levels, including programming sig- nals. Bit locations may be programmed singly, in biocks, or at random. The Am27H010 supports AMDs Flash- rite programming algorithm (100 ps pulses) resulting in typical programming time of 16 seconds. BLOCK DIAGRAM Oo* Vpp Oo Vss Oo Vcc Output Enable Chip Enable and al m Y Decoder A0-A16 Address Inputs X Decoder Data Outputs DQ0-DQ7 han aan Output Buffers 1,048,576-Bit Cell Matrix 12750D-1 Publication# 12750 Rev.D Amendment/d Issue Date: July 1993 3-21a\ AMD PRODUCT SELECTOR GUIDE Family Part No. Am27H010 Ordering Part No: Voc +5% -45V05 -90V05 Voc +10% -45 -55 -70 -90 Max Access Time (ns) 45 55 70 90 CE (E) Access (ns) 45 55 70 90 OE (G) Access (ns) 20 25 35 40 CONNECTION DIAGRAMS Top View DIP PLCC/LCC Vee [ 10 32 1} Vec Ais [}2 31 [] PGM (P) Ais I} 3 30 1] NC Ai2 [} 4 29 1] a14 A7 Os 28 [] A13 As []6 27 [] as AT A14 As []7 26 [] Ag AG A13 A4 [] 8 25 1] ait AS A8 A3 [J9 241] OE) A4 _ A3 Att A2 [] 10 23 1] A1o A2 OE ) At [11 22 [) CE) At Ato Ao [] 12 21 1] Daz AO CE (E) pao [J 13 20 [] Dae Dao DQ7 bat I] 14 49 LJ Das paz [J 15 18 [] Da4 Vss [] 16 17 1] Das 12750D-2 12750D-3 Note: 1. JEDEC nomenclature is in parentheses. PIN DESIGNATIONS LOGIC SYMBOL A0-A16 = Address Inputs CE (E) = Chip 17 DQ0-DQ7_ = Data Inputs/Outputs (7) AO-A16 NC = No Internal Connection OE (G) = Output Enable Input 8 PGM (P) == _- Program Enable Input DQo-DQ7 </> Vec = Vcc Supply Voltage cE ) Vep = Program Supply Voltage PGM ) Vss = Ground = j OF (G) 12750D-4 3-22 Am27H010ORDERING INFORMATION EPROM Products AMD al AMD Standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: AM27H010 -45 D LL OPTIONAL PROCESSING Blank = Standard Processing B Burn-In TEMPERATURE RANGE C = Commercial (0C to +70C) | Industrial (40C to +85C) Valid Combinations AM27H010-45 DC, DCB, DI, DIB, AM27H010-45V05 | LC, LI, LCB, LIB AM27H010-55 DC, DCB, DE, DEB, AM27H010-70 DI, DIB, LC, LCB, LI, AM27H010-90 LIB, LE, LEB E = Extended Commercial (-55C to +125C) PACKAGE TYPE D = 32-Pin Ceramic DIP (CDV032) L = 32-Pin Ceramic Leadless Chip Carrier (CLV032) SPEED OPTION See Product Selector Guide and Valid Combinations DEVICE NUMBER Am27H010 1 Megabit (131,072 x 8-Bit) High Speed CMOS EPROM Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Am27H010 3-23al AMD ORDERING INFORMATION OTP Products AMD Standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: AM27H010 55 P Cc LL OPTIONAL PROCESSING Blank = Standard Processing TEMPERATURE RANGE C = Commercial (0C to +70C) ACKAGE TYPE = 32-Pin Plastic DIP (PD 032) = 32-Pin Rectangular Plastic Leaded Chip Carrier (PL 032) P P J SPEED OPTION See Product Selector Guide and Valid Combinations DEVICE NUMBER Am27H010 1 Megabit (131,072 x 8-Bit) High Speed CMOS OTP EPROM Valid Combinations Valid Combinations AM27H010-55 Valid Combinations list configurations planned to AM27H010-70 be supported in volume for this device. Consult PC, JC the local AMD sales office to confirm availability of AM27H010-90 n : sas specific valid combinations and to check on newly AM27H010-90V05 released combinations. 3-24 Am27H010AMD al ORDERING INFORMATION Military APL Products AMD products for Aerospace and Defense applications are available in several packages and operating ranges. APL (Approved Products List) products are fully compliant with MIL-STD-883 requirements. The order number (Valid Combination) is formed by a combination of: AM27H010 -55 /B x A LL LEAD FINISH A = Hot Solder Dip PACKAGE TYPE X = 32-Pin Ceramic DIP (CDV032) U = 32-Pin Rectangular Ceramic Leadless Chip Carrier (CLV032) DEVICE CLASS /B = Class B SPEED OPTION See Product Selector Guide and Valid Combinations DEVICE NUMBER Am27H010 1 Megabit (131,072 x 8-Bit) High Speed CMOS EPROM Valid Combinations Valid Combinations AM27H010-55 Valid Combinations list configurations planned to be AM27H010-70 /BXA, /BUA supported in volume for this device. Consult the local AM27H010-90 AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Group A Tests Group A tests consist of Subgroups 1, 2, 3, 7, 8, 9, 10, 11. Am27H010 3-25at AMD FUNCTIONAL DESCRIPTION Erasing the Am27H010 In order to clear all locations of their programmed con- tents, it is necessary to expose the Am27H010 to an ultraviolet light source. A dosage of 15 W seconds/cm?is required to completely erase an Am27H010. This dos- age can be obtained by exposure to an ultraviolet lampwavelength of 2537 Awith intensity of 12,000 uW/cm? for 15 to 20 minutes. The Am27H010 should be directly under and about one inch from the source and all filters should be removed from the UV light source prior to erasure. It is important to note that the Am27H010 and similar devices will erase with light sources having wavelengths shorter than 4000 A. Although erasure times will be much longer than with UV sources at 25374, exposure to fluorescent light and sunlight will eventually erase the Am27H010 and exposure to them should be prevented to realize maximum system reliability. If used in such an environment, the package window should be covered by an opaque label or substance. Programming the Am27H010 Upon delivery or after each erasure the Am27H010 has all 1,048,576 bits in the ONE or HIGH state. ZEROs are loaded into the Am27H010 through the procedure of programming. The programming mode is entered when 12.75 V + 0.25 V is applied to the Vep, CE and PGM is at Vit and OE = Vin. For programming, the data to be programmed is applied 8 bits in parallel to the data output pins. The Fiashrite algorithm reduces programming time by using 100 1s programming pulses and by giving each address only as many pulses as is necessary in order to reliably program the data. After each pulse is applied to a given address, the data in that address is verified. If the data does not verify, additional pulses are given until it verifies or the maximum is reached. This process is re- peated while sequencing through each address of the Am27H010. This part of the algorithm is done at Vcc = 6.25 V to assure that each EPROM bit is programmed to a sufficiently high threshold voltage. After the final ad- dress is completed, the entire EPROM memory is veri- fied at Vcc = Vpp = 5.25 V. Please refer to Section 6 for programming flow chart and characteristics. Program Inhibit Programming of multiple Am27H010 in parallel with dif- ferent data is also easily accomplished. Except for CE, all like inputs of the parallel AM27H010 may be com- mon. A TTL low-level program pulse applied to an Am27H010 CE input and with Vep = 12.75 V + 0.25 V, PGM Low and OE High will program that Am27H010. A high-level CE input inhibits the other Am27H010 de- vices from being programmed. Program Verify Averify should be performed on the programmed bits to determine that they were correctly programmed. The verify should be performed with OE and CE at Vit, PGM at Vin and Vpp between 12.5 V and 13.0 V. Auto Select Mode The auto select mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25C + 5C ambient temperature range that is required when programming the Am27H010. To activate this mode, the programming equipment must force 12.0 V + 0.5 V on address line AQ of the Am27H010. Two identifier bytes may then be se- quenced from the device outputs by toggling address line AO from Vit to Vin. All other address lines must be held at Vi. during auto select mode. Byte 0 (AO = ViL) represents the manufacturer code, and byte 1 (AO = Vin), the device code. For the Am27H010, these two identifier bytes are given in the Mode Select Table. All identifiers for manufacturer and device codes will possess odd parity, with the MSB (DQ7) defined as the parity bit. Read Mode The Am27H010 has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Assuming that ad- dresses are stable, address access time (tacc) is equal to the delay from CE to output (toe). Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection. Data is available at the outputs toe after the falling edge of OE, assuming that CE has been LOW and addresses have been stable for at least tacc toe. Standby Mode The Am27H010 has a standby mode which reduces the maximum Vcc current to 50% of the active current. It is placed in standby mode when CE is at Vin. The amount of current drawn in standby mode depends on the fre- quency and the number of address pins switching. The Am27H010 is specified with 50% of the address lines 3-26 Am27H010toggling at 10 MHz. A reduction of the frequency or quantity of address lines toggling will significantly re- duce the actual standby current. Output OR-Tieing To accommodate multiple memory connections, a two- line control function is provided to allow for: @ Low memory power dissipation B Assurance that output bus contention will not occur It is recommended that CE be decoded and used as the primary device-selecting function, while OE/Vpep be made a common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in low-power standby mode and that the output pins are only active when data is desired from a particular memory device. AMD at System Applications During the switch between active and standby condi- tions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks is dependent on the out- put capacitance loading of the device. At a minimum, a 0.1-uF ceramic capacitor (high frequency, low inherent inductance) should be used on each device between Vcc and Vss to minimize transient effects. In addition, to overcome the voltage drop caused by the inductive ef- fects of the printed circuit board traces on EPROM ar- rays, a 4.7-uF bulk electrolytic capacitor should be used between Vcc and Vss for each eight devices. The loca- tion of the capacitor should be close to where the power supply is connected to the array. MODE SELECT TABLE [Mode Pins CE OE PGM AO AQ Vpp | Outputs Read Vit Vit Xx AQ AQ ViH Dour Output Disable : MIL VIH X X x ViH Hi-Z Standby (TTL) VIH X X X X VIH Hi-Z Program VIL VIH ViL X x Vpp DIN Program Verify VIL VIL VIH X X VPP Dour Program Inhibit ViH X X X X Vpp Hi-Z Auto Select | Manufacturer Code VIL VIL X VIL VH Vec 01H (Note 3) | Device Code Vit Vit X ViH Vu Vec OEH Notes: 1. Va=120Vt05V 2. X = Either Vie or Vit 3. AlA8 = A10-A18 = Vit 4 . The Am27H010 uses the same Flashrite algorithm as the Am27C010. Am27H010 3-27al AMD ABSOLUTE MAXIMUM RATINGS Storage Temperature OTP Products ................. ~65C to +125C All Other Products .............. 65C to +150C Ambient Temperature with Power Applied ............. 55C to +125C Voltage with Respect to Vss All pins except A9,Vep,Vcc ... -0.6Vto Voc +0.5V (Note 1) AQ and Vpp (Note 2)............ O0.6Vt0o+13.5V VOC Lecce eee ee 0.6 Vto +7.0V Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During transitions, the inputs may overshoot Vss to -2.0 V for pe- riods of up to 20 ns. Maximum DC voltage on input and I/O pins is Vcc + 0.5 V which may overshoot to Vcc + 2.0 Vfor periods up to 20ns. 2. For A9 and Vep the minimum DC input is -0.5 V. During transitions, A9 and Vep may overshoot Vss to -2.0 V for periods of up to 20 ns. A9 and Vep must not exceed 13.5 V for any period of time. Stresses above those listed under Absolute Maximum Rat- ings may cause permanent damage to the device. This is a stress rating only; functional operation of the-device at these or any other conditions above those indicated in the opera- tional sections of this specification is not implied. Exposure of the device to absolute maximum rating conditions for ex- tended periods may affect device reliability. OPERATING RANGES Commercial (C) Devices Case Temperature (Tc).......... 0C to +70C industrial (1) Devices Case Temperature (Tc)........ 40C to +85C Extended Commercial (E) Devices Case Temperature (Tc) ....... 55C to +125C Military (M) Devices Case Temperature (Tc)....... 55C to +125C Supply Read Voltages Vec for Am27H010-XXV05 ... +4.75Vto +5.25V Vcc for AmM27H010-XX0 ..... +4.50 V to +5.50 V Operating ranges define those limits between which the functionality of the device is guaranteed. 3-28 Am27H010DC CHARACTERISTICS over operating range unless otherwise specified (Notes 1, 2, 3 and 4) (for APL Products, Group A, Subgroups 1, 2, 3, 7 and 8 are tested unless otherwise noted) AMD al Parameter Symbol Parameter Description Test Conditions Min Max Unit VOH Output HIGH Voltage loH = -4 mA 2.4 V VoL Output LOW Voltage lo. =12mA 0.45 Vv VIH Input HIGH Voltage 2.0 Vcc + 0.5 Vv VIL Input LOW Voltage 0.5 +0.8 V lu Input Load Current VIN = 0 Vto +Vcc C/I Devices 1.0 E/M Devices 1.0 na ILo Output Leakage Current Vout = 0 V to +Vcc C/l Devices 10 WA E/M Devices 10 Icc1 Vcc Active Current CE = Vit, f = 10 MHz C/I Devices 50 (Note 3) lout = 0 mA E/M Devices 60 mA Icc2 Vcc Standby Current CE = ViH C/l Devices 25 mA E/M Devices 35 IPP Vep Current During Read CE = OE = Vit, Vep = Vcc 100 LA Notes: 1. 2 3. 4 Vcc must be applied simultaneously or before Vpp, and removed simultaneously or after Vep. . Caution: The Am27H010 must not be removed from (or inserted into) a socket when Vcc or Vpp is applied. Icc1 is tested with OE/Vep = Vin to simulate open outputs. . Minimum DC Input Voltage is -0.5 V. During transitions, the inputs may overshoot to -2.0 V for periods less than 20 ns. Maximum DC Voltage on output pins is Vec + 0.5 V, which may overshoot to Vec + 2.0 V for periods less than 20 ns. 80 60 70 ss 55 N NS = 60 ~ 50 5 ; IN 3 < 2 3 < P Pe 50 7 >e&4 ] Q wa qs B 40 B 40 30 35 1 5 10 15 20 25 30 -60 -40 -20 0 20 40 60 80 100 120 140 Frequency in MHz Temperature C 12750D-5 12750D-6 Figure 1. Typical Supply Current Figure 2. Typical Supply Current vs. Frequency vs. Temperature Vcc = 5.0 V, T = 25C Vee = 5.0 V, f = 10 MHz Am27H010 3-29cl AMD CAPACITANCE Parameter Test CDV032 CLV032 PD 032 PL 032 Symbol | Parameter Description Conditions Typ | Max| Typ | Max | Typ | Max | Typ | Max | Unit CIN Input Capacitance Vin = 0 6 12 6 12 8 12 8 12 pF Cout Output Capacitance VouT = 0 8 15 6 15 10 15 10 15 pF Notes: 1. This parameter is only sampled and not 100% tested. 2. Ta = +25C, f = 1 MHz. SWITCHING CHARACTERISTICS over operating range unless otherwise specified (Notes 1, 3 and 4) (for APL Products, Group A, Subgroups 9,10 and 11 are tested unless otherwise noted) Parameter Am27H010 Symbols Parameter -45V05 -90V05 JEDEC Standard Description Test Conditions -45 -55 -70 -90 Unit tavav tRoc Address to CE =OE = Vit LMin ns Output Delay CL =Ci: Max 45 55 70 90 ns tELav tcE Chip Enable to OE = VIL Min ns Output Delay CL =Cu Max 45 55 70 90 ns tGLav tOE F Output Enable to CE = VIL Min ns Output Delay CL =Cu Max 20 25 35 40 ns tEHQZ, tDF Chip Enable HIGH or Min 0 0 0 0 ns taHaz (Note 2) | Output Enable HIGH, | , _ ,, Max 20 25 35 40 ns whichever comes first, to Output Float tAXQx tOH Output Hold from Min 0 ) 0 0 ns Addresses, CE, Max ns or OE, whichever occurred first Notes: 1. Vcc must be applied simultaneously or before Vpp, and removed simultaneously or after Vpp. This parameter is only sampled and not 100% tested. 2 3. Caution: The Am27H010 must not be removed from (or inserted into) a socket or board when Vpp or Vcc is applied. 4 . Output Load: 1 TTL gate and C = CL Input Rise and Fall Times: 5 ns Input Pulse Levels: 0 V to 3 V. Timing Measurement Reference Level: 1.5 V for inputs and outputs 3-30 Am27H010AMD al SWITCHING TEST CIRCUIT Device Under Test Ri NN V. CL Ri = 1212 VL=1.9V CL1 = 30 pF 12750D-7 Ci2 = 5 pF SWITCHING TEST WAVEFORM 3V X Test Points X 5 OV Output 12750D-8 AC Testing: Inputs are driven at 3.0 V for a logic 1 and 0 V for a logic 0. Input pulse rise and fall times are < 5 ns. Am27H010 3-3161 amo KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Must Be Will Be Steady Steady May Will Be Change Changing from H to L from H to L May Will Be Change Changing from L to H from L to H Don't Care, Changing Any Change State Permitted Unknown Does Not Center Apply Line is High Impedence Off State KS000010 SWITCHING WAVEFORMS 3V -- Addresses 15V Addresses Valid 1.5V OV ---- CE \ -__ tte ye " OE \ 7 _ tDF tace toe >) *| (Note 2) _____ __ tOH High Z (Note 1) -_----- High Z Output q Valid Output ) y 5} a 12750D-9 Notes: 1. OE may be delayed up to tacc toe after the falling edge of the addresses without impact on tacc. 2. {DF is specified from OE or CE, whichever occurs first. 3-32 Am27H010