To our custo mers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corpor ation took over all the business of both
companies. Therefore, althoug h the old com pany name remains in this docum ent, it is a valid
Renesas Electronics document. W e appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
Notice
1. All information included in this document is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please
confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to
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2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights
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No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights
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3. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.
4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of
semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software,
and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by
you or third parties arising from the use of these circuits, software, or information.
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“Standard”: Computers; office equipment; communications equipment; test and measurement equipment; audio and visual
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Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
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contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
To all our customers
MITSUBISHI MICROCOMPUTERS
7630 Group
1
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DESCRIPTION
The 7630
g
roup is a sin
g
le chip 8-bit microcomputer desi
g
ned with
CMOS silicon
g
ate technolo
g
y.
Bein
g
equipped with a CAN (Controller Area Network) module cir-
cuit, the microcomputer is suited to drive automotive equipments.
The CAN module complies with CAN specification version 2.0, part
B and allows priority-based messa
g
e mana
g
ement.
In addition to the microcomputers simple instruction set, the ROM,
RAM and I/O addresses are placed in the same memory map to
enable easy pro
g
rammin
g
.
The built-in ROM is available as mask ROM or One Time PROM.
For development purposes, em ulator- and EP ROM-type m icroc om-
puters are available as well.
FEATURES
z
Basic machine-lan
g
ua
g
e instructions . . . . . . . . . . . . . . . . . .71
z
Minimum instruction execution time
(at 10 MHz oscillation frequency) . . . . . . . . . . . . . . . . . .0.2 µs
z
Memory size
ROM . . . . . . . . . . . . . . . . .16252 bytes (M37630M4T-XX XFP)
RAM . . . . . . . . . . . . . . . . . . .512 bytes (M37630M4T-XXXFP)
z
I/O ports
Pro
g
rammable I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
z
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . 24 sources, 24 vectors
z
Timers
16-bit Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 channels
8-bit Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 channels
z
Serial I/Os
Clock synchronous. . . . . . . . . . . . . . . . . . . . . . . . . . . 1 channel
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 channel
z
CAN module
(CAN specification version 2.0, part B) . . . . . . . . . . .1 channel
z
A-D converter. . . . . . . . . . . . . . . . . . . . . . . . 8-bits x 8 channels
z
Watchdo
g
timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
z
Clock Generatin
g
Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Built-in with internal feedback resistor
z
Power source volta
g
e
(at 10 MHz oscillation frequency). . . . . . . . . . . . . . .4.0 to 5.5 V
z
Power dissipation
In hi
g
h-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 mW
(at 8 MHz oscillation frequency, at 5 V power source volta
g
e)
z
Operatin
g
temperature ran
g
e. . . . . . . . . . . . . . . . . –4 0 to 85 °C
z
Packa
g
e. . . . . . . . . . . . . . . . . . . . . . . . . . . . 44QFP (44P6N-A)
APPLICATION
Automotive controls
Fig. 1 Pin configuration of M37630M4T–XXXFP
34 22
35 21
36 20
37 19
38 18
39 17
40 16
41 15
42 14
43 13
44 12
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
M37630M4T-XXXFP
M37630E4T-XXXFP
P17
P20/SIN
P21/SOUT
P22/SCLK
P23/SRDY
VSS
P24/URXD
P25/UTXD
P26/URTS
P27/UCTS
P30
P02/AN2
P01/AN1
P00/AN0
VREF
AVSS
VCC
XOUT
XIN
VSS
RESET
P47/KW7
P16/PWM
P15/CNTR1
P14/CNTR0
P13/TX0
P12/INT1
P11/INT0
P07/AN7
P06/AN6
P05/AN5
P04/AN4
P03/AN3
P31/CTX
P32/CRX
P33
P34
P40/KW0
P41/KW1
P42/KW2
P43/KW3
P44/KW4
P45/KW5
P46/KW6
Package type: 44P6N-A
PIN CONFIGURATION (TOP VIEW)
44-pin plastic molded QFP
2
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 2 Functional block diagram
2021222324252627
P0 (8)
19
8
28293031323334
P1 (7)
35363738404142
P2 (8)
43
441234
P3 (5)
1516 13 17 14 39 18
RAMROM
VREF input
I/O port P0I/O port P1I/O port P2I/O port P3
3
4
UART
4
Serial I/OCAN
2
56789
1011
P4 (8)
12
I/O port P4
key on
wake up
Clock generating circuit
A (8)
X (8)
Y (8)
S (8)
PCL (8)
PS (8)
PCH (8)
CPU Timer X (16)
Timer Y (16)
Timer 1 (8)
Timer 2 (8)
Timer 3 (8)
PWM
INT0, INT1
A-D Converter
2
Clock
output
XOUT
Clock
input
XIN
Reset
input
RESET VCC VSS AVSS
M37630MXT-XXXFP FUNCTIONAL BLOCK DIAGRAM (PACKAGE: 44P6N-A)
WDT
2
MITSUBISHI MICROCOMPUTERS
7630 Group
3
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
Table 1: Pin description
Pin Name Input/Output Description
VCC, VSS Power source
volta
g
ePower supply pins; apply 4.0 to 5.5 V to VCC and 0 V to VSS
AVSS Analo
g
power
source volta
g
eGround pin for A-D converter. Connect to VSS
RESET Reset input Input Reset pin. This pin must be kept at “L” level for more than 2 µs, to enter the reset
state. If the crystal or ceramic resonator requires more time to stabilize, extend the
“L” level period.
XIN Clock input Input Input and output pins of the internal clock
eneratin
circuit. Connect a ceramic or
quartz–crystal resonator between the XIN and XOUT pins. When an external clock
source is used, connect it to XIN and leave XOUT open.
XOUT Clock output Output
VREF Reference volt-
a
g
e input Input Reference volta
e input pin for A-D converter
P00/AN0—
P07/AN7I/O port P0 I/O CMOS I/O ports or analo
input ports
P11/INT0Input CMOS input port or external interrupt input port. The active ed
e (risin
or fallin
) of
external interrupts can be selected. This pin will be used as VPP pin durin
g
PROM
pro
rammin
of One Tim e PROM Versions.
P12/INT1CMOS I/O port or external interrupt input port. The active ed
e (risin
or fallin
) of
external interrupts can be selected.
P13/TX0CMOS I/O port or input pin used in the bi-phase counter mode
P14/CNTR0I/O p o rt P1 I /O CMOS I/O port or timer X i nput pin used for the event counter, pulse width measure-
ment and bi-phase counter mode
P15/CNTR1CMOS I/O port or timer Y input pin used for the event counter , pulse width and pulse
period measurement mode
P16/PWM CMOS I/O port or PWM output pin used in the PWM mode of timers 2 and 3
P17CMOS I/O port
P20/SIN
P21/SOUT
P22/SCLK
P23/SRDY
CMOS I/O ports or clock synchronous serial I/O pins
P24/URXD
P25/UTXD
P26/URTS
P27/UCTS
CMOS I/O ports or asynchronous serial I/O pins
P30CMOS I/O port
P31/CTX CMOS I/O port or CAN transmit data pin
P32/CRX CMOS I/O port or CAN receive data pin
P33—P34CMOS I/O port
P40/KW0—
P47/KW7I/O por t P 4 I/O CMOS I/O ports. These ports can be used for key-on wake-up when confi
ured as
inputs.
I/O port P2
I/O port P3
I/O
I/O
4
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PART NUMBERING
Fig. 3 Part numbering
Product M37630 M 4 T– XXX FP
Packa
g
e type
FP: 44P6N-A packa
g
e
FS: 80D0 packa
g
e
ROM number
Omitted in One Time PROM version (blank) and EPROM version
T: Automotive use
ROM/PROM size
4: 16384 bytes
The first 128 bytes and the last 4 bytes of ROM are reserved areas.
They cannot be used.
Memory ty pe
M: Mask RO M vers ion
E: EPROM or One Time PROM version
MITSUBISHI MICROCOMPUTERS
7630 Group
5
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION
Mitsubishi plans to expand the 7630
g
roup as follows:
Memory Type
Support mask ROM, One Time PROM and EPROM versions .
Memory Size
ROM/ PR O M size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 Kb ytes
RAM size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 bytes
Package
44P6N-A . . . . . . . . . . . . . . . . .0.8mm-pitch plastic molded QFP
80D0 . . . . . . . . . . .0.8mm-pitch ceramic LCC (EPROM version)
Fig. 4 Memory expansion plan
Currently supported products are listed below:
ROM
External
60K
48K
32K
28K
24K
20K
16K
12K
8K
384 512 640 768 896 1024
RAM size (bytes)
M37630M4T
M37630E4T
Under development
Mass product
Table 2: List of supported products
Product (P)RO M size (bytes)
ROM size for User ( ) RAM size (bytes) Packa
g
e Remarks
M37630M4T-XXXFP Mask ROM version
M37630E4T-XXXFP 16384 512 44P6N-A One Ti me PROM version
M37630E4FP (16252) One Time PROM version (blank)
M37630E4FS 80D0 EPROM version
As of March 1998
6
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)
The core of 7630
g
roup microcomputers is the 7600 series CPU.
This core is based on the standard instruction set of 740 series;
however the performance is improved by allowin
g
to execute the
same instructions as that of the 740 series in less cycles. Refer to
the 7600 Series Software Manual for details of the instruction set.
CPU Mode Register CPUM
The CPU mode re
g
ister contains the stack pa
g
e selection bit and
internal system clock selection bit. The CPU mode re
g
ister is allo-
cated to address 000016.
Fig. 5 Structure of CPU mode register
CPU mode re
g
ister (address 000016)
CPUM
Processor mode bits (set these bits to “00”)
b1 b0
0 0: Sin
g
le–chip mode
0 1: Not used
1 0: Not used
1 1: Not used
Stack pa
g
e selection bit
0 : 0 pa
g
e
1 : 1 pa
g
e
Not used (“0” when read, do not write “1”)
Internal system clock selection bit
0 : φ=f(XIN) divided by 2 (hi
g
h–speed mode)
1 : φ=f(XIN) divided by 8 (middle–speed mode)
Not used (“0” when read, do not write “1”)
70
MITSUBISHI MICROCOMPUTERS
7630 Group
7
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MEMORY
Special Function Register (SFR) Area
The special function re
g
ister (SFR) area contains the re
g
isters
relatin
g
to functions such as I/O ports and timers.
RAM
RAM is used for data stora
g
e and for stack area of subroutine calls
and interrupts.
ROM
ROM is used for storin
g
user’s pro
g
ram code as well as the inter-
rupt vector area.
Interrupt Vector Area
The interrupt vector area is for s torin
g
jump destination addresses
used at reset or when an interrupt is
g
enerated.
Zero Page
This area can be accessed most efficiently by means of the zero
pa
g
e addressin
g
mode.
Speci al Page
This area can be accessed m ost efficiently by means of the s pecial
pa
g
e addressin
g
mode.
Fig. 6 Memory map diagram
004016
000016
00FF16
006016
XXXX16
YYYY16
ZZZZ16
FF0016
FFCA16
FFFB16
FFFC16
FFFF16
SFR area
Not used
Reserved ROM area
Interrupt vector area
Reserved ROM area
Zero pa
g
e
Special pa
g
e
CAN
SFRs
RAM area
RAM si ze
(byte) Address
XXXX16
192 011F16
256 015F16
384 01DF16
512 025F16
640 02DF16
768 035F16
896 03DF16
1024 045F16
1536 06DF16
2048 085F16
ROM area
ROM size
(byte) Address
YYYY16
Address
ZZZZ16
4096 F00016 F08016
8192 E00016 E08016
12288 D00016 D08016
16384 C00016 C08016
20480 B00016 B08016
24576 A00016 A08016
28672 900016 908016
32768 800016 808016
36864 700016 708016
40960 600016 608016
45056 500016 508016
49152 400016 408016
53248 300016 308016
57344 200016 208016
61440 100016 108016
User RAM
ROM
086016
8
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
SPECIAL FUNCTION REGISTERS (SFR)
Fig. 7 Memory map of special register (SFR)
003016 CAN transmit control re
g
ister CTRM
003116 CA N bus timin
g
control re
g
ister 1 CBTCON1
003216 CAN bus timin
g
control re
g
ister 2 CBTCON2
003316 CAN acceptance code re
g
ister 0 CAC0
003416 CAN acceptance code re
g
ister 1 CAC1
003516 CAN acceptance code re
g
ister 2 CAC2
003616 CAN acceptance code re
g
ister 3 CAC3
003716 CAN acceptance code re
g
ister 4 CAC4
003816 CAN acceptance mask re
g
ister 0 CAM0
003916 CAN acceptance mask re
g
ister 1 CAM1
003A16 CAN acceptance mask re
g
ister 2 CAM2
003B16 CAN acceptance mask re
g
ister 3 CAM3
003C16 CAN acceptance mask re
g
ister 4 CAM4
003D16 CAN receive control re
g
ister CREC
003E16 CAN transmit abort re
g
ister CABORT
003F16 Reserved
004016 CAN transmit buffer re
g
ister 0 CTB0
004116 CA N transmit buffer re
g
ister 1 CTB1
004216 CAN transmit buffer re
g
ister 2 CTB2
004316 CAN transmit buffer re
g
ister 3 CTB3
004416 CAN transmit buffer re
g
ister 4 CTB4
004516 CAN transmit buffer re
g
ister 5 CTB5
004616 CAN transmit buffer re
g
ister 6 CTB6
004716 CAN transmit buffer re
g
ister 7 CTB7
004816 CAN transmit buffer re
g
ister 8 CTB8
004916 CAN transmit buffer re
g
ister 9 CTB9
004A16 CAN transmit buffer re
g
ister A CTBA
004B16 CAN transmit buffer re
g
ister B CTBB
004C16 CAN transmit buffer re
g
ister C CTBC
004D16 CAN transmit buffer re
g
ister D CTBD
004E16 Reserved
004F16 Reserved
005016 CAN receive buffer re
g
ister 0 CRB0
005116 CA N receive buffer re
g
ister 1 CRB1
005216 CAN receive buffer re
g
ister 2 CRB2
005316 CAN receive buffer re
g
ister 3 CRB3
005416 CAN receive buffer re
g
ister 4 CRB4
005516 CAN receive buffer re
g
ister 5 CRB5
005616 CAN receive buffer re
g
ister 6 CRB6
005716 CAN receive buffer re
g
ister 7 CRB7
005816 CAN receive buffer re
g
ister 8 CRB8
005916 CAN receive buffer re
g
ister 9 CRB9
005A16 CAN receive buffer re
g
ister A CRBA
005B16 CAN receive buffer re
g
ister B CRBB
005C16 CAN receive buffer re
g
ister C CRBC
005D16 CAN receive buffer re
g
ister D CRBD
005E16 Reserved
005F16 Reserved
000016 CPU mode re
g
ister CPUM
000116 Not used
000216 Interrupt request re
g
ister A IREQA
000316 Interrupt request re
g
ister B IREQB
000416 Interrupt request re
g
ister C IREQC
000516 Interrupt control re
g
ister A ICONA
000616 Interrupt control re
g
ister B ICONB
000716 Interrupt control re
g
ister C ICONC
000816 Port P0 re
g
ister P0
000916 Port P0 direction re
g
ister P0D
000A16 Port P1 re
g
ister P1
000B16 Port P1 direction re
g
ister P1D
000C16 Port P2 re
g
ister P2
000D16 Port P2 direction re
g
ister P2D
000E16 Port P3 re
g
ister P3
000F16 Port P3 direction re
g
ister P3D
001016 Port P4 re
g
ister P4
001116 Port P4 direction re
g
ister P4D
001216 Serial I/O shift re
g
ister SIO
001316 Serial I/O control re
g
ister SIOCON
001416 A-D conversion re
g
ister AD
001516 A-D control re
g
ister ADCON
001616 Timer 1 T1
001716 Timer 2 T2
001816 Timer 3 T3
001916 Timer 123 mode re
g
ister T123M
001A16 Timer XL TXL
001B16 Timer XH TXH
001C16 Timer YL TYL
001D16 Timer YH TYH
001E16 Timer X mode re
g
ister TXM
001F16 Timer Y mode re
g
ister TYM
002016 UART mode re
g
ister UMOD
002116 UART baud rate
g
enerator UBRG
002216 UART control re
g
ister UCON
002316 UART status re
g
ister USTS
002416 UART transmit buffer re
g
ister 1 UTBR1
002516 UART transmit buffer re
g
ister 2 UTBR2
002616 UART receive buffer re
g
ister 1 URBR1
002716 UART receive buffer re
g
ister 2 URBR2
002816 Port P0 pull-up control re
g
ister PUP0
002916 Port P1 pull-up control re
g
ister PUP1
002A16 Port P2 pull-up control re
g
ister PUP2
002B16 Port P3 pull-up control re
g
ister PUP3
002C16 Port P4 pull-up/down control re
g
ister PUP4
002D16 Interrupt polarity selection re
g
ister IPOL
002E16 Watchdo
g
timer re
g
ister WDT
002F16 Polarity control re
g
ister PCON
MITSUBISHI MICROCOMPUTERS
7630 Group
9
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
I/O PORTS
The 7630
g
roup has 35 pro
g
rammable I/O pins and one input pin
arran
g
ed in five I/O ports (ports P0 to P4). The I/O ports are con-
trolled by the correspondin
g
port re
g
isters and port direc tion re
g
is-
ters; each I/O pin can be controlled separately.
When data is read from a port confi
g
ured as an output port, the port
latch’s contents are read instead of the port level. A port confi
g
ured
as an input port becomes floatin
g
and its level can be read. Data
written to this port will affect the port latch only; the port remains
floatin
g
.
Refer to Structure of port- and port direction re
g
isters, Structure of
port I/Os (1) and Structure of port I/Os (2).
Fig. 8 Structure of port- and port direction regi sters
Port Pij direction control bit (j = 0 to 7)
0 : Port confi
g
ured as input
1 : Port confi
g
ured as output
Note : The direction control bits corresponding to P10, P11, P35, P36 and
P37are not used (“0” when read, do not write “1”). Port direction re-
gisters are undefined when read (write only).
70
Port Pi direction re
g
ister (i = 0 to 4) (address 000916 + 2 · i)
PiD
Port Pij control bit (j = 0 to 7)
0 : “L” level
1 : “H” level
Note : The control bits corresponding to P10, P35, P36 and P37 are not used
(“0” when read, do not write “1”).
70
Port Pi re
g
ister (i = 0 to 4) (address 000816 + 2 · i)
Pi
10
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 9 Structure of port I/Os (1)
(1) Ports P00/AN0 to P07/AN7
(2) Port P11/INT0
Data bus
Interrupt input
(3) Port P12/INT1
Data bus
Pull-up control bit
Port latch
Direction
register
Interrupt input
(4) Port P13/TX0
Data bus
Pull-up control bit
Port latch
direction
register
Timer bi-phase mode input
(5) Ports P14/CNTR0, P15/CNTR1
Data bus
Pull-up control bit
Port latch
Direction
register
Timer bi-phase mode input
(6) Port P16/PWM
Data bus
Pull-up control bit
Port latch
Direction
register
PWM output
PWM output enable
Data bus
Pull-up control bit
Port latch
Direction
register
ADC input Analog input selection
Analog input selection
MITSUBISHI MICROCOMPUTERS
7630 Group
11
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 10 Structure of port I/Os (2)
(13) Ports P25/UTXD, P26/URTS
(14) Port P31/CTX
(15) Port P32/CRX
Data bus
CAN dominant level control bit
Port latch
(16) Ports P40/KW0 to P47/KW7
Data bus
Pull-up control bit
Port latch
Direction
register
Transmission or reception** in
progress
Transmit or receive** enable bit
UTXD or URTS output
Data bus
Pull-up control bit
Port latch
Direction
register
CAN port selection bit
CTX output
Direction
register
Pull-up/down control bit
CAN interrupt
CRX input
Data bus
Key-on wake-up control bit
Port latch
Direction
register
Pull-up/down control bit
Key-on wake-up interrupt
(9) Port P21/SOUT
Data bus
Pull-up control bit
Port latch
Direction
register
SIO output
SIO port selection bit
Transmit complete signal
(10) Port P22/SCLK
Data bus
Pull-up control bit
Port latch
direction
register
SIO clock output
Clock selection bit
Port selection bit
External clock input
(11) Por t P23/SRDY
Data bus
Pull-up control bit
Port latch
Direction
register
SRDY output
SRDY output selection bit
(12) Ports P24/URXD, P27/UCTS
Data bus
Pull-up control bit
Port latch
Direction
register
Transmission or reception* in
progress
Transmit or receive* enable bit
URXD or UCTS input
(7) Ports P17, P3 0, P33, P34
Data bus
Pull-up control bit
Port latch
Direction
register
(8) Po rt P20/SIN
Data bus
Pull-up control bit
Port latch
Direction
register
SIO1 input
(*) for UCTS
(**) f or URTS
SIO Port Select
12
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Port Pull-up/pull-down Function
Each pin of ports P0 to P4 except P11 is equipped with a pro
g
ram-
mable pull-up transistor. P32/CRX and P40/KW0 to P47/KW7 are
equipped with pro
g
rammable pull-down transistors as well. The
pull-up function of P0 to P3 can be controlled by the cor respondin
g
port pull-up control re
g
isters (see Structure of port pull-up/down
control re
g
isters). The pull-up/down function of ports P32 and P4
can be controlled by the correspondin
g
port pull-up/pull-down re
g
is-
ters to
g
ether with the polarity control re
g
ister (see Structure of
polarity control re
g
ister).
Fig. 11 Structure of port pull- up/down control regist ers
Fig. 12 Structure of polarity control register
P3j pull-up transistor control bit (j = 0, 1)
P32 pull-up/down transistor control bit
P3j pull-up transistor control bit (j = 3, 4)
Not used (“0” when read, do not write “1”)
Pij pull-up transistor control bit (j = 0 to 7)
0 : Pull-up transistor disabled
1 : Pull-up transistor enabled
70
Port Pi pull-up control re
g
ister (address 002816 + i) (i = 0, 2)
PUP0, PUP2
70
Port P1 pull-up control re
g
ister (address 002916)
PUP1
70
Port P3 pull-up control re
g
ister (address 002B16)
PUP3
P4j pull-up/down transistor control bit (j = 0 to 7)
70
Not used (“0” when read, do not write “1”)
P1j pull-up transistor control bit (j = 2 to 7)
0 : Pull-up/down transistor disabled
1 : Pull-up/down transistor enabled
Port P4 pull-up/down control re
g
ister (address 002C16)
PUP4
Key-on wake-up polarity control bit
0 : Low level active
1 : Hi
g
h level active
CAN module dominant level control bit
0 : Low level dominant
1 : Hi
g
h level dominant
Not used (undefined when read)
70
Polarity control re
g
ister (address 002F16)
PCON
MITSUBISHI MICROCOMPUTERS
7630 Group
13
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Port Overvoltage Application
When confi
g
ured as input ports, P1 to P4 may be subjected to over-
volta
g
e (VI>V
CC) if the input current to the applicable port is limited
to the specified values (see “Table 8:”). Use a serial resistor of
appropriate size to limit the input current. To estimate the resistor
value, assume the port volta
g
e to be VCC at overvolta
g
e condition.
Notes:
• Subjectin
g
ports to overvolta
g
e may effect the supply volta
g
e.
Assure to keep VCC and VSS within the tar
g
et limits.
• Avoid to subject ports to overvolta
g
e causin
g
VCC to rise above
5.5 V.
• The overvolta
g
e condition causin
g
input current flowin
g
throu
g
h
the internal port protection circuits has a ne
g
ative effect on the
ports noise immunity. Therefore, careful and intense testin
g
of
the tar
g
et system’s noise immunity is required. Refer to the
“countermeasures a
g
ainst noise” of the correspondin
g
users
manual.
• Port P0 must not be subjected to overvolta
g
e conditions.
14
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
INTERRUPTS
There are 24 interrupts: 6 external, 17 internal, and 1 software.
Interrupt Control
Each interrupt except the BRK instruction interrupt has both an
interrupt request bit and an interrupt enable bit, and is controlled by
the interrupt disable fla
g
. An interrupt occurs when the correspond-
in
g
interrupt request and enable bits are “1” and the interrupt dis-
able fla
g
is “0”. Interrupt enable bits can be cleared or set by
software. Interrupt request bits can b e clear ed by software but can-
not be set by software. The BRK instruction interrupt and reset can-
not be disabled w ith any fla
g
or bit. The I fla
g
disables all interrupts
except the BRK instruction interrupt and reset. If several interrupt
requests occur at the same time, t he interrupt with the hi
g
hest prior-
ity is accepted first.
Interrupt Operation
Upon acceptance of an interrupt, the followin
g
operations are auto-
matically performed.
1. The processin
g
bein
g
executed is stopped.
2. The contents of the pro
g
ram counter and processor status
re
g
ister are automatically pushed onto the stack.
3. Concurrently with the push operation, the interrupt jump
destination address is read from the vector table into the
pro
g
ram counter.
4. The interrupt disable fla
g
is set and the correspondin
g
interrupt
request bit is cleared.
Notes on use
When the active ed
g
e of an external interrupt (INT0, INT1, CNTR0,
CNTR1, CWKU or KOI) is chan
g
ed, the correspondin
g
interrupt
request bit may also be set. Therefore, take the followin
g
sequence.
(1) Disable the external interrupt which is selected.
(2) Chan
g
e the active ed
g
e in interrupt ed
g
e selection re
g
ister.
(in the case of CNTR0: Timer X mode re
g
ister; in the case of
CNTR1: Timer Y mode re
g
ister)
(3) Clear the interrupt request bit to “0”.
(4) Enable the external interrupt which is selected.
MITSUBISHI MICROCOMPUTERS
7630 Group
15
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
.
Table 3: Interrupt vector addresses and priority
Interrupt source Priority Vector Address (Note 1) Interrupt Request Generatin
g
Conditions Remarks
Hi
g
h Low
Reset (Note 2) 1FFFB16 FFFA16 A t Rese t Non-maskable
Watchdo
g
time r 2 FFF916 FFF816 At Watchdo
g
timer underflow Non-maskable
INT03FFF716 FFF616 At detection of either risin
g
or fallin
g
ed
g
e of INT0 interrupt Extern al Interrupt
(active ed
g
e selectable)
INT14FFF516 FFF416 At detection of either risin
g
or fallin
g
ed
g
e of INT1 interrupt Extern al Interrupt
(active ed
g
e selectable)
CAN successful
transmit 5FFF316 FFF216 At CAN module successful
transmission of messa
g
eValid when CAN module is
activated and request transmit
CAN successful
receive 6FFF116 FFF016 At CAN module successful reception
of messa
g
eValid when CAN module is
activated
CAN overrun 7 FFEF16 FFEE16 If CAN module receives messa
g
e
when receive buffers are full. Va lid when CAN module is
activated
CAN error
passive 8FFED16 FFEC16 When CAN module enters into error
passive st ate Valid when CAN module is
active
CAN error bus off 9 FFEB16 FFEA16 When CAN module enters into bus
off state Valid when CAN module is
active
CAN wake up 10 FFE916 FFE816 When CAN module wakes up via
CAN bus
T imer X 11 FFE716 FFE616 At Timer X underflow or overflow
T imer Y 12 FFE516 FFE416 At Timer Y underflow
T imer 1 13 FFE316 FFE216 A t Timer 1 underflow
T imer 2 14 FFE116 FFE016 At Timer 2 underflow
T imer 3 15 FFDF16 FFDE16 At Timer 3 underflow
CNTR016 FFDD16 FFDC16 At detection of either risin
g
or fallin
g
ed
g
e in CNTR0 input Extern al Interrupt
(active ed
g
e selectable)
CNTR117 FFDB16 FFDA16 At detection of either risin
g
or fallin
g
ed
g
e in CNTR1 input Extern al Interrupt
(active ed
g
e selectable)
UART receive 18 FFD916 FFD816 At completion of UART receive Valid when UART is selected
UART transmit 19 FFD716 FFD616 At completion of UART transmit Valid when UART is selected
UART transmit
buffer empty 20 FFD516 FFD416 At UART transmit buffer empty Va lid when UART is selected
UART receive
error 21 FFD316 FFD216 When UART reception error occurs. Valid when UART is selected
Serial I/O 22 FFD116 FFD016 At completion of serial I/O data
transmit and receive Valid when serial I/O is
selected
A-D conversion 23 FFCF16 FFCE16 At completion of A-D conversion
Key-on wake-up 24 FFCD16 FFCC16 At detection of either risin
g
or fallin
g
ed
g
e of P4 input Extern al Interrupt
(active ed
g
e selectable)
BRK instruction 25 FFCB16 FFCA16 At BR K instruction execution Non-maskable
Notes 1: Vector addresses contain interrupt jump destination address
2: Reset function in the same way as an interrupt with the hi
g
hest priority
16
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 13 Interrupt control
Fig. 14 Structure of interrupt polarity selection register
BRK instruction
Reset
Interrupt disable flag I
Interrupt request bit
Interrupt enable bit
Interrupt request
Not used (returns to “0” when read, do not write “1” in this bit)
INT0 interrupt ed
g
e selection bit
INT1 interrupt ed
g
e selection bit
Not used (returns to “0” when read, do not write “1” in these bits)
70
Interrupt polarity selection re
g
ister (Address 002D16)
IPOL
0 : Fallin
g
ed
g
e active
1 : Risin
g
ed
g
e active
For the external interrupts INT0 and INT1, the active ed
g
e causin
g
the interrupt request can be selected by the INT0 and INT1 interrupt
ed
g
e selection bits of the interrupt polarity selection re
g
ister (IPOL);
please refer to Fi
g
. 14 below.
MITSUBISHI MICROCOMPUTERS
7630 Group
17
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 15 Structure of interrupt request and control registers A, B and C
7Interrupt request re
g
ister A
(address 000216)
IREQA
CAN wake up
interrupt request bit
Timer X interrupt request bit
Timer Y interrupt request bit
Timer 1 interrupt request bit
Timer 2 interrupt request bit
Timer 3 interrupt request bit
CNTR0 interrupt request bit
CNTR1 interrupt request bit
70
70
0 : No interrupt request
1 : Interrupt requested
0
Not used
(returns to ”0” when read)
External interrupt INT0 request bit
External interrupt INT1 request bit
CAN successful transmission
interrupt request bit
CAN successful receive
interrupt request bit
CAN overrun interrupt request bit
CAN error passive
interrupt request bit
CAN bus off interrupt request bit
Interrupt request re
g
ister B
(address 000316)
IREQB
Interrupt request re
g
ister C
(address 000416)
IREQC
UART receive complete
(receive buffer full)
interrupt request bit
UART transmit complete
(transmit re
g
ister empty)
interrupt request bit
UART transmit buffer empty
interrupt request bit
UART receive error interrupt
request bit
Serial I/O interrupt request bit
AD conversion complete
interrupt request bit
Key-on wake-up interrupt request bit
Not used (returns to ”0” when read)
70
Not used (returns to ”0” when read)
External interrupt INT0 enable bit
External interrupt INT1 enable bit
CAN successful transmission
interrupt enable bit
CAN successful receive
interrupt enable bit
CAN overrun interrupt enable bit
CAN error passive
interrupt enable bit
CAN bus off interrupt enable bit
Interrupt control re
g
ister A
(address 000516)
ICONA
7 0
Interrupt control re
g
ister B
(address 000616)
ICONB
CAN wake–up interrupt enable bit
Timer X interrupt enable bit
Timer Y interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
Timer 3 interrupt enable bit
CNTR0 interrupt enable bit
CNTR1 interrupt enable bit
7 0
Interrupt control re
g
ister C
(address 000716)
ICONC
UART receive complete
(receive buffer full)
interrupt enable bit
UART transmit complete
(transmit re
g
ister empty)
interrupt enable bit
UART transmit buffer empty
interrupt enable bit
UART receive error interrupt
enable bit
Serial I/O interrupt enable bit
AD conversion complete
interrupt enable bit
Key-on wake-up interrupt enable bit
Not used (returns to ”0” when read)
0: Interrupt disabled
1: Interrupt enabled
18
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
KEY-ON WAKE-UP
“Key-on wake-up” is one way of returnin
g
from a power-down state
caused by the STP or WIT instruction. Any terminal of port P4 can
be used to
g
enerate the key-on wake-up interrupt request. The
active polarity can be selected by the key-on wake-up polarity con-
trol bit of PCON (see Fi
g
. 12). If any pin of port P4 has the selected
active level applied, the key-on wake-up interrupt request will be set
to “1”. Please refer to Fi
g
. 16.
Fig. 16 Block diagram of key-on wake-up circuit
PUP4j
key-on wake-up interrupt
key-on wake-up control bit
P4Dj
port P4j I/O circuit
…
port P4j/KWj
j = 0 to 7
MITSUBISHI MICROCOMPUTERS
7630 Group
19
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMERS
The 7630
g
roup has five timers: two 16-bit timers and three 8-bit
timers . All these timers will be described in detail below. 16-bit Timers
Timers X and Y are 16-bit timers with multiple operatin
g
modes.
Plea se ref er to Fi
g
. 17.
Fig. 17 Block diagram of timers X and Y (φ is internal system clock)
Timer X
Timer X is a 16-bit timer with a 16-bit reload latch supportin
g
the fol-
lowin
g
operatin
g
modes:
(1) Timer mode
(2) Bi-phase counter mode
(3) Event counter mode
(4) Pulse width measurement mode
These modes can be s elected by the timer X mode r e
g
ister (TXM ).
In the timer- and pulse width measurement mode, the timer’s count
source can be selected by the timer X count source selection bits of
the timer Y mode re
g
ister (TYM). Please refer to the Fi
g
ures below
for the TXM and TYM bit assi
g
nment.
On read or write access to timer X, note that the hi
g
h-order and low-
order bytes must be accessed in the specific order.
Write method
When writin
g
to the timer X, write the low-order byte first. The data
written is stored in a temporary re
g
ister which is assi
g
ned to the
same address a s TXL. Next, write the hi
g
h-order byte. When this is
finished, the data is placed in the timer X hi
g
h-order reload latch
and the low-order byte is transferred from its temporary re
g
ister to
the timer X low-order reload latch. Dependin
g
on the timer X write
control bit, the latch contents are reloaded to the timer immediately
(write control bit = “0”) or on the next timer underflow (write control
bit = “1”).
Read method
When readin
g
the timer X, read the hi
g
h-order byte first. This
causes the timer X hi
g
h- and low-order bytes to be transferred to
temporary re
g
isters bein
g
assi
g
ned to the same addresses as TXH
and TXL. Next, read the low-order byte w hich is read from the tem-
porary re
g
ister. This method ass ures the c orrect timer v alue can b e
read durin
g
the timer count operation.
Timer X count stop control
Re
g
ardless of the actual operatin
g
mode, timer X can be stopped
by settin
g
the timer X count stop bit (bit 7 of the timer X mode re
g
is-
ter) to “1”.
TYM5, 4=“11”
TYM7
1/16
1/64
1/128
TYM1,0
φ
P13/TX0
P14/CNTR0
edge detector
edge detector
sign generator
TXL counter (8)
TXH latch (8)
TXH counter (8)
TXM7TXL latch (8)
count
direction
control
TXM5, 4
down
“00”, “10”,
“11”
“01”
“00”, “11”
“01”
“10”
TXM6
TXM5, 4=“11”
TX interrupt request
CNTR0 interrupt request
1/8
1/32
1/64
P15/CNTR1
TYM6
TYM5, 4
“10”
“0x”, “11” TYL counter (8)
TYH latch (8)
TYH counter (8)
TYL latch (8)
TY interrupt request
CNTR1 interrupt request
rising edge detector
falling edge detector
TYM5, 4=“01”
TYM5, 4
“11”
“0x”, “10”
“0”
“1”
TYM3, 2
1/4
1/2
TXM5,4
“00”
“01”
“10”
“11”
“00”
“01”
“10”
“11”
“0”
“1”
20
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 18 Structure of Timer X mode register
Timer Y
Timer Y is a 16 bit timer with a 16-bit reload latch supportin
g
the fol-
lowin
g
operatin
g
modes:
(1) Timer mode
(3) Event counter mode
(5) Pulse period measurement mode
(6) H/L pulse width measurement mode
These modes can be s elected by the timer Y mode r e
g
ister (TYM ).
In the timer, pulse period- and pulse width measurement modes’
the timer’s count source can be selected by the timer Y count
source selection bits. Please refer to Fi
g
. 19.
On read or write access to timer Y, note that the hi
g
h-order and low-
order bytes must be accessed in a specific order.
Write method
When writin
g
to timer Y, write the low-order byte first. The data writ-
ten is stored in a temporary re
g
iste r wh ic h is assi
g
ned to the same
address as TYL. Next, write the hi
g
h-order byte. When this is fin-
ished, the data is placed in the timer Y hi
g
h-order reload latch and
the low-order byte is transferred from its temporary re
g
ister to the
timer Y low-order reload latch.
Read method
When readin
g
the timer Y, read the hi
g
h-order byte first. This
causes the timer Y hi
g
h- and low-order bytes to be transferred to
temporary re
g
isters bein
g
assi
g
ned to the same addresses as TYH
and TYL. Next, read the low-order byte w hich is read from the tem-
porary re
g
ister. This method ass ures the c orrect timer v alue can b e
read durin
g
timer count operation.
Timer Y count stop control
Re
g
ardless of the actual operatin
g
mode, timer Y can be stopped
by settin
g
the timer Y count stop bit (bit 7 of the timer Y mode re
g
is-
ter) to “1”.
Timer X data write control bit
0 : Data is written to latch and timer
1 : Data is written to latch only
Not used (“0” when read, do not write “1”)
Timer X mode bits
b5 b4
0 0: Timer mode
0 1: Bi-phase counter mode
1 0: Event counter mode
1 1: Pulse width measurement mode
CNTR0 polarity selection bit
0 : For event counter mode, risin
g
ed
g
e active
For interrupt request, fallin
g
ed
g
e active
For pulse width measurement mode, measure “H” period
1 : For event counter mode, fallin
g
ed
g
e active
For interrupt request, risin
g
ed
g
e active
For pulse width measurement mode, measure “L” period
Timer X stop control bit
0 : Timer countin
g
1 : Timer stopped
70
Timer X mode re
g
ister (address 001E16)
TXM
MITSUBISHI MICROCOMPUTERS
7630 Group
21
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 19 Structure of timer Y mode register (φ is internal system clock)
Operatin
g
Modes
(1) Timer mode
This mode is available with timer X and timer Y.
• Count source
The count source for timer X and Y is the output of the corre-
spondin
g
clock divider. The division ratio can b e selected by the
timer Y mode re
g
ister.
• Operation
Both timers X and Y are down counters. On a timer underflow,
the correspondin
g
timer interrupt request bit will be set to “1”, the
contents of the correspondin
g
timer latches will be reloaded to
the counters and countin
g
continues.
(2) Bi-phase counter mode (quadruplicate)
This mode is available with timer X only.
• Count source
The count sources are P14/CNTR0 and the P13/TX0 pins.
• Operation
T imer X will count both risin
g
and fallin
g
ed
g
es on both input pins
(see above). Refer to Timer X bi-phase counter mode operation
for the timin
g
chart of the bi-phase counter mode.
The count direction is determined by the ed
g
e polarity and level
of count source inputs and may chan
g
e durin
g
the count opera-
tion. Refer to the table below.
On a timer over- or underflow, the correspondin
g
interrupt
request bit will be set to “1” and countin
g
continues.
Timer X count source selection bits
b1 b0
0 0: φ divided by 4
0 1: φ divided by 16
1 0: φ divided by 64
1 1: φ divided by 128
Timer Y count source selection bits
b3 b2
0 0: φ divided by 2
0 1: φ divided by 8
1 0: φ divided by 32
1 1: φ divided by 64
Timer Y operation mode bits
b5 b4
0 0: Timer mode
0 1: Pulse period measurement mode
1 0: Event counter mode
1 1: H/L pulse width measurement mode
CNTR1 polarity selection bit
0 : For event counter mode, risin
g
ed
g
e active
For interrupt request, fallin
g
ed
g
e active
For pulse period measurement mode, refer to fallin
g
ed
g
es
1 : For event counter mode, fallin
g
ed
g
e active
For interrupt request, risin
g
ed
g
e active
For pulse period measurement mode, refer to risin
g
ed
g
es
Timer Y stop control bit
0 : Timer countin
g
1 : Timer stopped
70
Timer Y mode re
g
ister (address 001F16)
TYM
Table 4: Timer X count direction in Bi-phase counter mode
P13/TX0P14/CNTR0Count direction
↑ Ed
g
eLUp
H Down
↓ Ed
g
eL Down
HUp
L
↑ Ed
g
eDown
HUp
L
↓ Ed
g
eUp
H Down
22
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 20 Timer X bi-phase counter mode operation
(3) Event counter mode
This mode is available with timer X and timer Y.
• Count source
The count source for timer X is the input si
g
nal to the P14/CNTR0
pin and for timer Y the input si
g
nal to P15/CNTR1 pin.
• Operation
The timer counts down. On a timer underflow, the correspondin
g
timer interrupt request bit will be set to “1”, the contents of the
correspondin
g
timer latches will be reloaded to the counters and
countin
g
continues. The active ed
g
e used for countin
g
can be
selected by the polarity selection bit of the correspondin
g
pin
P14/CNTR0 or P15/CNTR1. These bits are part of TXM (Structure
of Timer X mode re
g
ister) and TYM (Structure of timer Y mode
re
g
ister (f is internal system clock)) re
g
isters.
(4) Pulse width measurement mode
This mode is available with timer X only.
• Count source
The count source is the output of timer X clock divider. The divi-
sion ratio can be selected by the timer Y mode re
g
ister.
• Operation
The timer counts down while the input si
g
nal level on
P14/CNTR0 matches the active polarity selected by the CNTR0
polarity selection bit of TXM (Structure of Timer X mode re
g
is-
ter). On a timer underflow, the timer X interrupt request bit will be
set to “1”, the contents of the timer latches are reloaded to the
counters and countin
g
continues. When the input level chan
g
es
from active polarity (as selected), the CNTR0 interrupt request bit
will be set to “1.” The measurement result may be obtained by
readin
g
timer X durin
g
interrupt service.
(5) Pulse period measurement mode
This mode is available with timer Y only.
• Count source
The count source is the output of timer Y clock divider.
• Operation
The active ed
g
e of input si
g
nal to be measured can be selected
by CNTR1 polarity selection bit (Fi
g
. 18). When this bit is set to
“0”, the time between two consecutive fallin
g
ed
g
es of the si
g
nal
input to P15/CNTR1 pin will be measured, when the polarity bit is
set to “1”, the time between two consecutive risin
g
ed
g
es will be
measured.
The timer counts down. On detection of an active ed
g
e of input
si
g
nal, the contents of the TY counters will be transferred to tem-
porary re
g
isters assi
g
ned to the same addresses as TY. At the
same time, the contents of TY latches will be reloaded to the
counters and countin
g
continues. The acti ve ed
g
e of input si
g
nal
also causes the CNTR1 interrupt request bit to be set to “1”. The
measurement result may be obtained by readin
g
timer Y durin
g
interrupt service.
(6) H/L pulse width measurement mode
This mode is available with timer Y only.
• Count source
The count source is the output of the timer Y’s clock divider.
• Operation
This mode measures both the “H” and “L” periods of a si
g
nal
input to P15/CNTR1 pin continuously. On detection of any ed
g
e
(risin
g
or fallin
g
) of input si
g
nal to P15/CNTR1 pin, the contents of
timer Y counters are stored to temporary re
g
isters which are
assi
g
ned to the same addresses as timer Y. At the same time,
the contents of timer Y latches are reloaded to the counters and
countin
g
continues. The detection of an ed
g
e causes the
CNTR1 interrupt request bit to be set to “1” as well. The result of
measurement may be obtained by readin
g
timer Y dur in
g
inter-
rupt serv ice. This read access will address the temporary re
g
is-
ters. On a timer underflow, the timer Y interrupt request bit will
be set to “1”, the contents of timer Y latches will be transferred to
the counters and countin
g
continues.
P13/TX0 input si
g
nal
P14/CNTR0 input si
g
nal
TX counter
count direction down up
MITSUBISHI MICROCOMPUTERS
7630 Group
23
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMER 1, TIMER 2, TIMER 3
Timers 1 to 3 are 8-bit timers with 8-bit reload latches and one com-
mon pre-divider. Timer 1 can operate in the timer mode only, whereas timers 2 and 3 can be used to
g
enerate a PWM output si
g
-
nal timin
g
as well. Timers 1 to 3 are down count timers. See Fi
g
. 21.
Fig. 21 Block diagram of timers 1 to 3 (φ is internal system clock)
Timer 1
The count source of timer 1 is the output of timer 123 pre-divider.
The division ratio of the pre-divider can be selected by the pre-
divider division ratio bits of timer 123 mode re
g
ister (T123M). Refer
to Ti mer 123 mode re
g
ister confi
g
uration (f is internal system clock).
On a timer 1 underflow, the timer 1 interrupt request bit will be set to
“1”.
Writin
g
to timer 1 initializes the latch and counter.
Timers 2 and 3
The count source of timers 2 and 3 can be either the output of the
timer 123 pre-divider or the timer 1 underflow. The count source can
be selected by the timer count source selection bits of timer 123
mode re
g
ister (T123M).
Writin
g
to timer 2 re
g
ister affects the reload latch only or both of the
reload latch and counter dependin
g
on the timer 2 write control bit
of T123M. When the timer write control bit is set to “0”, both latch
and counter will be initialized simultaneously; when set to “1” only
the reload latch will be initialized, on an underflow, the counter will
be set to the modified reload value. Writin
g
to timer 3 initializes
latch and counter both.
Timer 2 or 3 underflow caus es the timer 2 or 3 interrupt request bit
to be set to “1”.
T123M0
1
1/8
1/32
1/128
T123M67
φ
T1 counter (8)
T1 latch (8)
T2 counter (8)
T2 latch (8)
T3 counter (8)
T3 latch (8)
T1 interrupt
T2 interrupt
T3 interrupt
S
RQ
S
RQ
T123M3
T123M4
T123M1
T123M1
S
TQ
P16/PWM P16 latch
P1D6
T123M1
“00”
“01”
“10”
“11”
“1” “0”
“0” “1”
“1” “0”
“0” “1”
24
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 22 Timer 123 mode register configuration (φ is internal system clock)
Operating Modes
(1) Timer Mode
This mode is available with timers 1 to 3.
• Count source
For timer 1, the count source is the output of the correspondin
g
pre-divider. For timers 2 and 3, the count source can be sepa-
rately selected to be either the pre-divider output or timer 1
underflow.
• Operation
The timer counts down. On a timer underflow, the correspondin
g
timer interrupt request bit will be set to “1”, the contents of the
correspondin
g
timer latch will be reloaded to the counter and
countin
g
continues.
(2) PWM Mode
This mode is available with timer 2 and 3.
• Count source
The count source can be separately selected to be either the
pre-divider output or timer 1 underflow.
• Operation
When the PWM-mode is enabled, timer 2 starts countin
g
. As
soon as timer 2 underflows, timer 2 stops and timer 3 starts
countin
g
. If bit 0 is set, timer 2 determines the low duration and
the initial output level is low. Timer 3 determines the hi
g
h dura-
tion. If bit 0 is zero timer 2 determines the hi
g
h duration and the
initial output level is hi
g
h. In this case timer 3 determines the low
duration.
Note: Be sure to confi
g
ure the P16/PWM pin as an output port
before usin
g
PWM mode.
PWM polarity selection bit
0 : Start on “H” level output
1 : Start on “L” level output
PWM output enable bit
0 : PWM output disabled
1 : PWM output enabled
Timer 2 write control bit
0 : Latch and counter
1 : Latch only
Timer 2 count source selection bit
0 : Timer 1 underflow
1 : Pre-divider output
Timer 3 count source selection bit
0 : Timer 1 underflow
1 : Pre-divider output
Not used (“0” when read, do not write “1”)
Pre-divider division ratio bits
b7 b6
0 0: φ divided by 1
0 1: φ divided by 8
1 0: φ divided by 32
1 1: φ divided by 128
70
Timer 123 mode re
g
ister (address 001916)
T123M
MITSUBISHI MICROCOMPUTERS
7630 Group
25
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
SERIAL I/Os
The serial I/O section of 7630
g
roup consists of one clock synchro-
nous and one asynchronous (UART) interface.
Clock Synchronous Serial I/O (SI/O)
The clock synchronous interface allows full duplex communication
based on 8 bit word len
g
th. The transfer clock can be selected from
an internal or external clock. When an internal clock is selected, a
pro
g
rammable clock divider allows ei
g
ht different transmission
speeds. Refer to Block dia
g
ram of clock synchr onous I/O (f is inter-
nal system clock). The operation of the clock synchronous serial I/O
can be confi
g
ured by the serial I/O control re
g
ister S IOCON; r efer to
Fi
g
. 25.
Fig. 23 Block diagram of clock synchronous I/O (φ is internal system clock)
(1) Clock synchronous serial I/O operation
Either an internal or external transfer clock can be selected by bit 6
of SIOCON. The int ernal clock di vider can be pro
g
rammed by bits 0
to 2 of SIOCON. Bit 3 of SIOCON determines whether the double
function pins P20 to P22 will act as I/O ports or serve as SIO pins.
Bit 4 of SIOCON allows the same selection for pin P23.
When an internal transfer clock is selected, transmission can be
tri
gg
ered by writin
g
data to the SI/O shift re
g
ister (SIO, address
001216). After an 8–bit transmission has been completed, the SOUT
pin will chan
g
e to hi
g
h impedance and the SIO interrupt request bit
will be set to “1”.
When an external transfer clock is selected, the SIO interrupt
request bit will be set to “1” after 8 cycles but the contents of the
SI/O shift re
g
ister continue to be shifted while the transfer clock is
bein
g
input. Therefore, the clock needs to be controlled externally;
the SOUT pin will not chan
g
e to hi
g
h impedance automatically.
SIOCON2, 1, 0
φ
SIO interrupt
Sync. circuit
P23 latch
P22/SCLK
P23/SRDY
P22 latch
SIO counter (3)
P21/SOUT
P21 latch
SIO shift register (8)
P20/SIN
P20 latch
SIOCON4
SIOCON3
SIOCON3
SIOCON3
SIOCON6
Clock divider
“0” “1” “0”
“0”
“0”
“0”
“1”
“1”
“1”
“1”
26
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 24 Timing of clock synchronous SI/O function (LSB first selected)
Fig. 25 Structure of serial I/O control register (φ is internal system clock)
Clock Asynchronous Serial I/O (UART)
The UART is a full duplex asynchronous transmit/receive unit. The
built-in clock divider and b aud rate
g
enerator enable a broad ran
g
e
of transmission speeds. Please refer to Block dia
g
ram of UART.
(1) Description
The transmit and receive s hift re
g
isters have a buffer (consistin
g
of
hi
g
h and low order byte) each. Since the shift re
g
isters cannot be
written to or read from directly, transmit data is written to the trans-
mit buffer and receive data is read from the receive buffer. A trans-
mit or receive operation will be tri
gg
ered by the transmit enable bit
and receive enable bit of the UART control re
g
ister UCON (see
Structure of UART control re
g
ister). The double function terminals
P25/UTXD, P26/URTS and P24/URXD, P27/UCTS will be switched to
serve as UART pins automatically.
D0D1D2D3D4D5D6D7
D0D1D2D3D4D5D6D7
Serial input SIN
Serial Out put SO UT
write signal to SIO
receive enable signal SRDY
transfer clock
SIO interrupt request bit = “1”
Note: When an internal clock is selected, SOUT pin will change to high impedance after 8 bits of data have been transmitted.
synchronous clock
Clock divider selection bits
b2 b1 b0
0 0 0: φ divided by 4
0 0 1: φ divided by 8
0 1 0: φ divided by 16
0 1 1: φ divided by 32
1 0 0: φ divided by 64
1 0 1: φ divided by 128
1 1 0: φ divided by 256
1 1 1: φ divided by 512
P20/SIN, P2 1/SOUT and P22/SCLK function selection bit
0 : I/O port function
1 : SI/O function
P23/SRDY function selection bit
0 : I/O port function
1 : SI/O function
Transmission order selection bit
0 : LSB firs t
1 : MSB first
Synchronization clock selection bit
0 : use external clock
1 : use internal clock
Not used (“0” when read)
70
SIO control re
g
ister (address 001316)
SIOCON
MITSUBISHI MICROCOMPUTERS
7630 Group
27
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(2) Baud rate selection
The baud rate of transmission and reception is determined by the
settin
g
of the prescaler and the contents of the UART baud rate
g
enerator re
g
ister. It is calculated by: where
p
is the division ratio of
the prescaler and
n
is the content of UART baud rate
g
enerator re
g
-
ister. The prescalers division ration can be selected by the UART
mode re
g
ister (see below).
UART mode register (UMOD, Structure of UART
mode register)
The UART mode re
g
ister allows to select the transmission and
reception format with the followin
g
options:
• word len
g
th: 7, 8 or 9 bits
• parity: none, odd or even
• stop bits: 1 or 2
It allows to select the prescalers division ratio as well.
UART baud rate generator (UBRG)
This 8 bit re
g
ister allows to select the baud rate of the UART (see
above). Set this re
g
ister to the desired value before enablin
g
recep-
tion or transmission.
UART control register (UCON, Structure of UART
control register)
The UART control re
g
ister consists of four control bits (bit 0 to bit 3)
which allow to control reception and transmission.
UART status register (USTS, Structure of UART
status register)
The read-only UART status re
g
ister consists of 7 bits (bit 0 to bit 6)
which indicate the operatin
g
status of the UART function and vari-
ous errors.
(3) Handshaking signals
When used as transmitter the UART will reco
g
nize the clear-to-
send si
g
nal via P27/UCTS terminal for handshakin
g
. When used as
receiver it will issue a request-to-send si
g
nal throu
g
h P26/URTS
pin.
Clear-to-send in put
When used as a transmitter (transmit enable bit set to “1”), the
UART starts transmission after reco
g
nizin
g
“L” level on P27/UCTS.
After started the UART will continue to transmit re
g
ardless of the
actual level of P27/UCTS or status of the transmit enable bit.
Request-to-send output
The UART controls the P26/URTS output accordin
g
to the followin
g
conditions.
Table 5: Output control conditions
Fig. 26 Block diagram of UART
bφ
16 pn1+()⋅⋅
-----------------------------------
=
Condition P26/URTS
Receive enable bit is set to “1” “L”
Reception completed durin
g
receive enable
bit set to “1”
Start bit (fallin
g
ed
g
e) detected
“H”
Receive enable bit is set to “0” before recep-
tion started
Hardware reset
Receive initialization bit is set to “1”
UMOD4,3,2
φ
1
1/8
1/32
1/256
UMOD2, 1
UBRG (8) transmit shift register (9)
transmission
control circuit
reception control
circuit
P25/UTXD
P27/UCTS
P26/URTS
bit counter
bit counter
UMOD7, 6
UMOD7, 6
UART status register
transmit buf fer empty fl ag
receive error flags
receive buffer full interrupt request
receive error interrupt request
P24/URXD
transmi t buffer (9)
data bus
data bus
transmit buffer empty interrupt request
transmit register empty interrupt request
receive buffer full flag
transmit register empty flag
receive shift register (9)
receive buffer (9)
UART control register
“00”
“01”
“10”
“11”
28
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 27 Structure of UART mode register
Fig. 28 Structure of UART control register
Not used (“0” when read, do not write “1”)
clock divider selection bits
b2 b1
0 0 : φ divided by 1
0 1 : φ divided by 8
1 0 : φ divided by 32
1 1 : φ divided by 256
Stop bits selection bit
0 : One stop bit
1 : Two stop bits
Parity selection bit
0 : Even parity
1 : Odd parity
Parity enable bit
0 : Parity disabled
1 : Parity enabled
UART word len
g
th selection bits
b7 b6
0 0 : 7 bits
0 1 : 8 bits
1 0 : 9 bits
1 1 : Not used
70
UART mode re
g
ister
UMOD (address 002016)
Transmit enable bit
0 : Transmit disabled (an on
g
oin
g
transmission will be finished correctly)
1 : Transmit enabled
Receive enable bit
0 : Receive disabled (an on
g
oin
g
reception will be finished correctly)
1 : Receive enabled
Transmission initialization bit
0 : No action
1 : Clear transmit buffer full fla
g
and transmit shifter full fla
g
, set the
transmit status re
g
ister bits and stop transmission
Receive initialization bit
0 : No action
1 : Clear receive status fla
g
s and the receive enable bit
Not used (“0” when read, do not write “1”)
70
UART control re
g
ister
UCON (address 002216)
MITSUBISHI MICROCOMPUTERS
7630 Group
29
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 29 Structure of UART status register
Transmit re
g
ister empty fla
g
0 : Re
g
ister full
1 : Re
g
ister empty
Transmit buffer empty fla
g
0 : Buffer full
1 : Buffer empty
Receive buffer full fla
g
0 : Buffer full
1 : Buffer empty
Receive parity error fla
g
0 : No parity error detected
1 : Parity error detected
Receive framin
g
error fla
g
0 : No framin
g
error detected
1 : Framin
g
error detected
Receive overru n fla
g
0 : No overrun detected
1 : Overrun detected
Receive error sum fla
g
0 : No error detected
1 : Error detected
Not used (“0” when read)
Note: this re
g
ister is read only; writin
g
does not affect its contents.
70
UART status re
g
ister (address 002316)
USTS
30
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
CAN MODULE
The CAN (Controller Area Network) interface of the 7630
g
roup
complies with the 2.0B specifica tion, enablin
g
reception and trans-
mission of frames with either 11- or 29- bit identifier len
g
th. Refer to
Fi
g
. 31 for a block dia
g
ram of the CAN interface.
The pro
g
rammer ’s interface to the CAN m odule is formed by three
status/control re
g
isters (Fi
g
. 32, Fi
g
. 33, Fi
g
. 34), two bus timin
g
control re
g
isters (Fi
g
. 35 Fi
g
. 36), several re
g
isters for acceptance
filterin
g
(Fi
g
. 37), the transmit and receive buffer re
g
isters (Fi
g
. 38)
and one dominant level control bit (Fi
g
. 22).
Baud Rate Selection
A pro
g
rammable clock prescaler is used to derive the CAN mod-
ule’s basic clock from the internal system clock frequency (φ). Bit 0
to bit 3 of the CAN bus timin
g
control re
g
ister represent the pres-
caler allowin
g
a division ratio from 1 to 1/16 to be selected. So the
CAN module basic clock frequency fCANB can be calculated as fol-
lows:
where
p
is the value of the prescaler (selectable from 1 to 15). The
effective baud rate of the CAN bus communication depends on the
CAN bus timin
g
control parameters and will be explained below.
CAN Bus Timing Control
Each bit-time consists of four different se
g
ments (see Fi
g
. 30):
• Synchronization se
g
ment (SS),
• Propa
g
ation time se
g
ment (PTS),
• Phase buffer se
g
ment 1 (PBS1) and
• Phase buffer se
g
ment 2 (PBS2).
Fig. 30 Bit time of CAN module
The first of these se
g
ments is of fixed len
g
th (one Time Quantum)
and the latter three can be pro
g
rammed to be 1 to 8 Time Quanta
by the CAN bus timin
g
control re
g
ister 1 and 2 (see Fi
g
. 35 and Fi
g
.
36). The whole bit-time has to consist of minimum 8 and maximum
25 Time Quanta. The duration of one Time Quantum is the cycle
time of fCANB. For example, assumin
g
φ= 5 MHz, p = 0, one Time
Quantum will be 200 ns lon
g
. This allows the maximum transmis-
sion rate of 625 kb/s to be reached (assumin
g
8 Time Quanta per
bit-time).
Fig. 31 Block diagram of CAN module
f
CANB φ
p1+
------------
=
SS
PTS
PBS1
PBS2
Sample point
Bit-time
bus timing control
register
data bus
acceptance mask
register acce pta nce code
register
transmit buffer
receive buffer 1
receive buffer 2
acceptance filter
data bus
P31/CTX
P32/CRX protocol controller
CAN wake-up
wake-up logic
polarity cont rol
register CAN status/control
registers
MITSUBISHI MICROCOMPUTERS
7630 Group
31
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 32 Structure of CAN transmit control register
70
CAN transmit control re
g
ister (address 003016)
CTRM
Sleep control bit
0 : CAN module in normal mode
1 : CAN module in sleep mode
Reset/confi
g
uration control bit
0 : CAN module in normal mode
1 : CAN module in confi
g
uration mode (plus reset at write)
Port double function control bit
0 : P31/CTX serves as I/ O port
1 : P31/CTX serves as CTX output port
Transmit request bit
0 : No transmission requested
1 : Transmission requested
(write “0” has no effect)
Not used (no operation, “0” when read)
Transmit buffer control bit
0 : CPU access possible
1 : No CPU access
(write “0” has no effect, while CTRM(3) = 1)
Not used (no operation, “0” when read)
Transmit status bit (read only)
0 : CAN module idle or receivin
g
1 : CAN module transmittin
g
32
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 33 Structure of CAN receive control register
Fig. 34 Structure of CAN transmit abort register
70
CAN receive control re
g
ister (address 003D16)
CREC
Receive buffer control bit
0 : Receive buffer empty
1 : Receive buffer full
(write “1” has no effect)
Receive status bit (read only)
0 : CAN module idle or transmittin
g
1 : CAN module receivin
g
Not used (do not write “1”, read as “0”)
Auto-receive disable bit
0 : Auto-receive enabled
1 : Auto-receive disabled
Note: Suppresses reception of self initiated/transmitted frames
Not used (do not write “1”, “0” when read)
70
CAN transmit abort re
g
ister (address 003E16)
CABORT
Transmit Abort control bit
0 : No Transmit Abort Request
1 : Transmit Abort Request
(write “1” has no effect, while CTRM(3) = 0)
Not used (No operation, “0” when read)
MITSUBISHI MICROCOMPUTERS
7630 Group
33
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 35 Structure of CAN bus timing control register 1
Fig. 36 Structure of CAN bus timing control register 2
70
CAN bus timin
g
control re
g
ister 1 (address 003116)
CBTCON1
Prescaler division ratio selection bits
b3 b2 b1 b0
0 0 0 0: φ divided by 1
0 0 0 1: φ divided by 2
0 0 1 0: φ divided by 3
…
1 1 1 0: φ divided by 15
1 1 1 1: φ divided by 16
Samplin
g
control bit
0 : One sample per bit
1 : Three sample per bit
Propa
g
ation time duration control bits
b7 b6 b5
0 0 0: One Time Quantum
0 0 1: Two Time Quanta
…
1 1 0: S even Time Quanta
111:Ei
g
ht Time Quanta
70
CAN bus timin
g
control re
g
ister 2 (address 003216)
CBTCON2
Phase buffer se
g
ment 1 duration control bits
b2 b1 b0
0 0 0: One Time Quantum
0 0 1: Two Time Quanta
…
1 1 0: S even Time Quanta
111:Ei
g
ht Time Quanta
Phase buffer se
g
ment 2 duration control bits
b5 b4 b3
0 0 0: One Time Quantum
0 0 1: Two Time Quanta
…
1 1 0: S even Time Quanta
111:Ei
g
ht Time Quanta
Synchronization jump width control bits
b7 b6
0 0 : O ne Time Quantum
0 1 : Two Time Quanta
1 0 : Three T ime Quanta
1 1 : Four Time Quanta
34
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 37 Structure of CAN mask and code registers
Fig. 38 Structure of CAN transmission and reception buffer registers
address
7 0
Not used Not used Not used CSID10 CSID9CSID8CSID7CSID6
CSID5CSID4CSID3CSID2CSID1CSID0Not used Not used
Not used Not used Not used Not used CEID17 CEID16 CEID15 CEID14
CEID13 CEID12 CEID11 CEID10 CEID9CEID8CEID7CEID6
CEID5CEID4CEID3CEID2CEID1CEID0Not used Not used
7 0
Not used Not used Not used MSID10 MSID9MSID8MSID7MSID6
MSID5MSID4MSID3MSID2MSID1MSID0Not used Not used
Not used Not used Not used Not used MEID17 MEID16 MEID15 MEID14
MEID13 MEID12 MEID11 MEID10 MEID9MEID8MEID7MEID6
MEID5MEID4MEID3MEID2MEID1MEID0Not used Not used
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
Acceptance code
registers:
Acceptance mask
registers:
Select the bit pattern of identifiers which allows to pass acceptance filterin
g
.
0 : Mask identifier bit (do not care)
1 : Compare identifier bit with acceptance code re
g
ister bit
(Not used: write to “0”)
name
CAC0
CAC1
CAC2
CAC3
CAC4
CAM0
CAM1
CAM2
CAM3
CAM4
offset
7 0
Not used Not used Not used SID10 SID9SID8SID7SID6
SID5SID4SID3SID2SID1SID0RTR/SRR IDE
Not used Not used Not used Not used EID17 EID16 EID15 EID14
EID13 EID12 EID11 EID10 EID9EID8EID7EID6
EID5EID4EID3EID2EID1EID0RTR r1
000016
000116
000216
000316
000416
Not used Not used Not used r0DLC3DLC2DLC1DLC0000516
000616
data byte 0
000716
data byte 1
000816
data byte 2
000916
data byte 3
000A16
data byte 4
000B16
data byte 5
000C16
data byte 6
000D16
data byte 7
Calculate the actual address as follows:
TxD buffer address = 004016 + offset
RxD buffer address = 005016 +offset
(Not used: write to “0”)
name
CTB0, CRB0
CTB1, CRB1
CTB2, CRB2
CTB3, CRB3
CTB4, CRB4
CTB5, CRB5
CTB6, CRB6
CTB7, CRB7
CTB8, CRB8
CTB9, CRB9
CTBA, CRBA
CTBB, CRBB
CTBC, CRBC
CTBD, CRBD
Note 1: All CAN related SFRs must not be written in “CAN sleep” mode.
MITSUBISHI MICROCOMPUTERS
7630 Group
35
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A-D CONVERTER
The A-D converter uses the succes sive approximation method with
8 bit resolution. The functional blocks of the A-D converter are
described below. Refer to Block dia
g
ram of A-D converter.
Comparison Voltage Generator
The comparison volta
g
e
g
enerator divides the volta
g
e between
AVSS and VREF by 256, and outputs the divided volta
g
e.
Channel Selector
The channel selector selects one of ports P00/AN0 to P07/AN7, and
inputs its volta
g
e to the comparator.
A-D conversion register AD
The A-D conversion re
g
ister is a read-only re
g
ister that stores the
result of an A-D conversion. This re
g
ister must not be read durin
g
an A-D conversion.
Fig. 39 Block diagram of A-D converter
A-D control register (Structure of A-D control reg-
ister)
The A-D control re
g
ister controls the A-D conversion process. Bits 0
to 2 select a specific analo
g
input pin. Bit 3 si
g
nals the completion
of an A-D conversion. The value of this bit remains “ 0” durin
g
an A-
D conversion, and chan
g
es to “1” when an A-D conversion ends.
Writin
g
“0” to this bit starts the A-D conversion. Bit 4 is the VREF/
Input switch bit.
AVSS
P00/AN0
3
A-D control register b7 b0
comparison voltage
generator
A-D control circuit
Comparator
P07/AN7
VREF
A-D interrupt request
A-D conversion register
channel selector
Data bus
VREF/Input switch bit
36
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 40 Structure of A-D control register
A-D Converter Operation
The comparator and control circuit reference an analo
g
input volt-
a
g
e with the reference volta
g
e, then stores the result in the A-D
conversion re
g
ister. When an A-D conversion is com plete, the con-
trol circuit sets the A-D conversion completion bit and the A-D inter-
rupt request bit to “1”. The result of A-D conversion can be obtained
from the A-D conversion re
g
ister, AD (address 001416).
Note that the comparator is linked to a capacitor , so set f(X IN) t o 500
kHz or hi
g
her durin
g
A-D conversion.
70
A-D control re
g
ister (address 001516)
ADCON
Analo
g
input pin selection bits
b2 b1 b0
0 0 0 : P00/AN0
0 0 1 : P01/AN1
0 1 0 : P02/AN2
0 1 1 : P03/AN3
1 0 0 : P04/AN4
1 0 1 : P05/AN5
1 1 0 : P06/AN6
1 1 1 : P07/AN7
A-D conversion completion bit
0 : Conversion in pro
g
ress
1 : Conversion completed
VREF/Input switch bit
0 : Off
1 : On
Not used (“0” when read, do not write “1”)
MITSUBISHI MICROCOMPUTERS
7630 Group
37
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
WATCHDOG TIMER
The watchdo
g
timer consists of two separate counters: one 7-bit
counter (WDH) and one 4-bit counter (WDL). Cascadin
g
both
counters or usin
g
the hi
g
h-order counter allows only to select the
time-out from either 524288 or 32768 cycles of the internal clock φ.
Refer to Fi
g
. 41 and Fi
g
. 42. Both counters are addressed by the
same watchdo
g
timer re
g
ister (WDT). When writin
g
to this re
g
ister,
both counters will be set to the followin
g
default values:
•the hi
g
h-order counter will be set to address 7F16
• the low-order counter will be set to address F16
re
g
ardless of the data written to the WDT re
g
ister. Readin
g
the
watchdo
g
timer re
g
ister will return the correspon din
g
control bit sta-
tus, not the counter contents.
Once the WDT re
g
ister is written to, the watchdo
g
timer starts
countin
g
down and the watchdo
g
timer interrupt is enabled. Once it
is runnin
g
, the watchdo
g
timer cannot be disabled or stopped
except by reset. On a watchdo
g
timer underflow, a non-maskable
watchdo
g
timer interrupt will be requested.
To prevent the system bein
g
stopped by STP instruction, this
instruction can be disabled by the STP instruction disable bit of
WDT re
g
ister. Once the STP instruction is disabled, it cannot be
enabled a
g
ain except by RESET.
Fig. 41 Block diagram of watchdog timer
Fig. 42 Structure of watchdog timer register (φ is internal clock system)
1/256
φ
WDT interrupt
WDL counter (4) WDH counter (7)
WDT7
“F16”“7F
16”
WDT register (8)
“0”
“1”
Not used (undefined when read)
Stop instruction disable bit
0 : Stop instruction enabled
1 : Execute two NOP instructions instead (once this bit is set to
“1” it can not be cleared to “0” a
g
ain, except on RESET.)
Upper byte count source selection bit
0 : Underflow of the low order counter
1 : φ divided by 256
70
Watchdo
g
timer re
g
ister (address 002E16)
WDT
38
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
RESET CIRCUIT
The 7630
g
roup is reset accordin
g
to the sequence shown in Fi
g
.
44. It starts pro
g
ram execution from the address formed by the con-
tents of the addresses FFFB16 and FFFA16, when the RESE T pin is
held at “L” level for more than 2 µs while the power supply volta
g
e is
in the recommended operatin
g
condition and then returned to “H”
level.
Refer to Fi
g
. 43 for an example of the reset circuit.
Fig. 43 Example of reset circuit
Fig. 44 Reset sequence
power on
0V
0V
power source voltage
reset input voltage
4.0V
0.8V
7630 group
M51953AL
RESET
VSS
VCC
0.1µF
1
5
4
3
XIN
RESET
internal reset
Address
Data ?????
?????
28 to 34
cycles of XIN
ADLADH
FFFA16 FFFB16 ADL, ADH
1st op code
20 cycles of XIN
24 cycles of XIN
8192 cycles of
XIN (T1, T2)
…
MITSUBISHI MICROCOMPUTERS
7630 Group
39
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 45 Internal status of microcomputer after reset
Register Address Register contents
T imer XH 001B16 FF16
T imer YL 001C16 FF16
T imer YH 001D16 FF16
Timer X mode reg. 001E16 0016
Timer Y mode reg. 001F16 0016
UART mode reg. 002016 0010
UART control reg. 002216 0016
UART status reg. 002316 0710
Port P0 pull-up control reg. 002816 0016
Port P1 pull-up control reg. 002916 0016
Port P2 pull-up control reg. 002A16 0016
Port P3 pull-up control reg. 002B16 0016
Port P4 pull-up/down control reg. 002C16 0016
Interrupt polarity selection reg. 002D16 0016
Watchdog timer reg. 002E16 3F16
Polarity control reg. 002F16 0016
CAN transmit control reg. 003016 0216
CAN bus timing control reg. 1 003116 0016
CAN bus timing control reg. 2 003216 0016
CAN receive control reg. 003D16 0016
CAN transmit abort reg. 003E16 0016
Processor status reg. (PS) 0416
Program counter (high-order byte) (PCH) content s of FFFB16
Program counter (low-order byte) (PCL) contents of FFFA16
Register Address Register contents
CPU mode reg. 000016 4816
Interrupt request reg. A 000216 0016
Interrupt request reg. B 000316 0016
Interrupt request reg. C 000416 0016
Interrupt control reg. A 000516 0016
Interrupt control reg. B 000616 0016
Interrupt control reg. C 000716 0016
Port P0 reg. 000816 0016
Port P0 direction reg. 000916 0016
Port P1 reg. 000A16 0016
Port P1 direction reg. 000B16 0016
Port P2 reg. 000C16 0016
Port P2 direction reg. 000D16 0016
Port P3 reg. 000E16 0016
Port P3 direction reg. 000F16 0016
Port P4 reg. 001016 0016
Port P4 direction reg. 001116 0016
Serial I/O control reg. 001316 0016
A-D control reg. 001516 0816
Timer 1 001616 FF16
Timer 2 001716 0116
Timer 3 001816 FF16
Timer 123 mode reg. 001916 4016
Timer X L 001A16 FF16
Note: The contents of RAM and re
g
isters other than the above re
g
isters are undefined after reset; thus software initialization is required.
40
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
CLOCK GENERATING CIRCUIT
The 7630
g
roup is equipped with an internal clock
g
eneratin
g
cir-
cuit.
Please re fer to Fi
g
. 46 for a circuit example usin
g
a ceramic resona-
tor or quartz crystal oscillator. For the capacitor values, refer to the
manufacturers recommended parameters which depend on each
oscillators characteristics. When usin
g
an external clock, input it to
the XIN pin and leave XOUT open.
Fig. 46 Ceramic resonator circuit .
Oscillation Control
The 7630
g
roup has two low power modes: the stop and the wait
mode.
Stop m ode
The microcomputer enters the stop mode by executin
g
the STP
instruction. The oscillator stops with the internal clock φ at “H” level.
Timers 1 and 2 will be cascaded and initialized by their reload
latches contents. The count source for timer 1 will be set to
f(XIN)/16.
Oscillation is restarted if an external interrupt is accepted or at
reset. When usin
g
an external interrupt, the internal clock φ remains
at “H” level until timer 2 underflows allowin
g
a time-out until the
clock oscillation becomes stable. When usin
g
reset, a fixed time-out
will be
g
enerated allowin
g
oscillation to stabilize.
Wait mode
The microcomputer enters the wait mode by executin
g
the WIT
instruction. The internal clock ø stops at “H” level while the osci llator
keeps runnin
g
.
Recovery from wait mode can be done in the same way as from
stop mode. However, the time-out period mentioned above is not
required to return from wait-mode, thus no such time-out mecha-
nism has been implemented.
Note: Set the interrupt enable bit of the interrupt source to be used
to return from stop or wait mode to “1” before executin
g
STP or WIT
instruction.
Fig. 47 Block diagram of clock generating circuit
C
IN
C
OUT
X
IN
X
OUT
WIT
STP
XIN
XOUT
1/2
1/4
CPUM6
interrupt request
interrupt disable flag S
R
Q
RESET
delaySTP
D
T
Q
D
T
QR
S
Q
R
S
Q
R
S
Q
STP
P2
internal clock
for
peripherals
internal clock
for CPU
oscillator countdown
(timer 1 and 2)
2
φ
φ
“1”
“0”
MITSUBISHI MICROCOMPUTERS
7630 Group
41
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DATA REQUIRED FOR MASK ORDERS
The followin
g
are necessary when orderin
g
a mask ROM produc-
tion:
1 Mask ROM Order Confirmation Form
2 Mark Specification Form
3 Contents of Mask ROM, in EPROM form (three identical
copies)
PROM PROGRAMMING METHOD
The built-in PROM of the blank One Time PROM version and built-
in EPROM version can be read or pro
g
rammed with a
g
eneral pur-
pose PROM pro
g
rammer usin
g
a special pro
g
rammin
g
adapter . Set
the address of PROM pro
g
rammer to the user ROM area.
For the pro
g
rammin
g
adapter type name, please refer to the follow-
in
g
table:
The PROM of the blank One Time PROM version is not tested or
screened in the assembly process and followin
g
processes. To
ensure proper operation after pro
g
rammin
g
, the procedure shown
in Fi
g
. 48 is recommended to verify pro
g
rammin
g
.
Fig. 48 Programming and testing of One Time PROM version
Table 6: Programming adapter name
MCU type Packa
g
ePro
g
rammin
g
adapter type
One Ti me
PROM 44P6N-A PCA7430
EPROM 80D0 PCA7431
Programming with PROM programmer
Screening *(Note)
(150
°
C for 40 hours)
Verification with PROM programmer
Functional test in target unit
Note on screening:
The screening temperature is far higher than the storage temper-
ature. Never subject the device to 150
°
C exceeding 100 hours.
42
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 7: ABSOLUTE MAXIMUM RATINGS
Table 8: RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Conditions Ratin
g
sUnit
V
CC Power source volta
g
e
All volta
g
es with respect to VSS
and output transistors are “off”.
–0 .3 to 7 .0 V
VI
Input volta
g
eP0
0
—P07, P11—P17,
P20—P27, P30—P34,
P40—P47, RESET, XIN
–0.3 to VCC + 0.3 V
VO
Output volta
g
eP0
0
—P07, P12—P17,
P20—P27, P30—P34,
P40—P47, XOUT
–0.3 to VCC + 0.3 V
PdPower dissipation Ta = 25 °C 500 mW
Topr Operatin
g
temperature –40 to 85 °C
Tstg Stora
g
e temperature –60 to 150 °C
Symbol Parameter Limits Unit
min. typ. max.
VCC Power source volta
g
e4.0 5.0 5.5 V
VSS 0V
V
IH “H” Input volta
g
eP00—P07, P11—P17, P20—P27,
P30—P34, P40—P47, RESET, XIN 0.8 · VCC VCC V
VIL “L” Input volta
g
eP00—P07, P11—P17, P20—P27,
P30—P34, P40—P47, RESET, XIN 00.2 · VCC V
∑ IOH (peak) “H” sum peak output current P00—P07, P12—P17, P20—P27,
P30—P34, P40—P47–80 mA
∑ IOH (av
g
)“H” sum avera
g
e output current –40 mA
∑ IOL (peak) “L” sum peak output current 80 mA
∑ IOL (av
g
)“L” sum avera
g
e output current 40 mA
IOH (peak) “H” peak output current –10 mA
IOH (av
g
)“H” avera
g
e output current –5 mA
IOL (peak) “L” peak output current 10 mA
IOL (av
g
)“L” avera
g
e output current 5mA
I
IO
input current at overvolta
g
e condi-
tion
(VI > VCC)
P11—P17, P20—P27,
P30—P34, P4 0—P471mA
∑
IIO
total input current at overvolta
g
e
condition
(VI > VCC)
P11—P17, P20—P27,
P30—P34, P4 0—P4716 mA
f(CNTR) Timer input frequency
(based on 50 % duty)
P14/CNTR0, P15/CNTR1
(except bi-phase counter mode) f(XIN)/16 MHz
P13/TX0, P14/CNTR0
(bi-phase counter mode) f(XIN)/32 MHz
f(XIN)Clock input oscillation frequency 10 M Hz
(VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V, Ta = – 40 to 85 °C unless otherwise noted)
MITSUBISHI MICROCOMPUTERS
7630 Group
43
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 9: ELECTRICAL CHARACTERISTICS
Symbol Parameter Te st conditions Limits Unit
min. typ. max.
VOH “H” output volta
g
e P00—P07, P12—P17,
P20—P27, P30—P34,
P40—P47
IOH = –5 mA 0.8 · VCC V
VOL “L” output volta
g
eP00—P07, P12—P17,
P20—P27, P30—P34,
P40—P47
IOL = 5 mA 2.0 V
VT+ – VT– Hysteresis
P11/INT0, P12/INT1,
P13/TX0, P14/CNTR0,
P15/CNTR1,P20/SIN,
P22/SCLK, P26/URTS,
P27/UCTS, P32/CRX,
RESET
0.5 V
IIH “H” input current P00—P07, P11—P17,
P20—P27, P30—P34,
P40—P47, RESET VI = VCC 5µA
IIH “H” input current XIN VI = VCC 4µA
IIL “L” input current P00—P07, P11—P17,
P20—P27, P30—P34,
P40—P47, RESET VI = VSS –5 µA
IIL “L” input current XIN VI = VSS –4 µA
IIH “H” input current P32,
P40—P47
VI = VCC
Pull-Down = ’On’ 20 200 µA
IIL “L” input current P00—P07, P11—P17,
P20—P27, P30—P34,
P40—P47, RESET
VI = VSS
Pull-Up = ’On’ -200 -20 µA
VRAM RAM hold volta
g
eWhen clock stopped 2.0 V
(VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V, Ta = – 40 to 85 °C unless otherwise noted)
44
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ICC Power source current
high speed mode,
f(XIN)=8MHz, V
CC =5V,
output transistors off,
CAN module running,
ADC running
11.0 18.0 mA
high speed mode,
f(XIN)=8MHz, V
CC =5V,
output transistors off,
CAN module stopped,
ADC running
9.0 16.0 mA
middle speed mode,
f(XIN)=8MHz, V
CC =5V,
output transistors off,
CAN module running,
ADC running
6.0 11.0 mA
middle speed mode, wait
mode, f(XIN)=8MHz,
V
CC = 5V, output transis-
tors off, CAN module
stopped, ADC stopped
2.0 mA
stop mode, f(XIN)=0MHz,
V
CC =5V, T
a=25
°
C0.1 1.0 µA
stop mode, f(XIN)=0MHz,
V
CC =5V, T
a=85
°
C10.0 µA
Symbol Parameter Te st conditions Limits Unit
min. typ. max.
Table 10: A-D converter characteristics
Symbol Parameter Test conditions Limits Unit
min. typ. max.
— Resolution 8Bit
— Absolute accuracy ±1.0 ±2.5 LSB
tCONV Conversion time high–speed mode 106 108 tC(XIN)
middle–s peed mode 424 432 tC(XIN)
VREF Reference input volta
g
e2.0
V
CC V
IREF Reference input current VCC = VREF = 5.12 V 150 200 µA
RLADDER Ladder resistor value 35 kΩ
IIAN Analo
g
input current VI = VSS to VCC 0.5 5.0 µA
(VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)
MITSUBISHI MICROCOMPUTERS
7630 Group
45
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 1 1: Timing requirements
Symbol Parameter Limits Unit
min. typ. max.
tW(RESET) Reset input “L” pulse width 2µs
tC(XIN)External clock input cycle time 100 ns
tWH(XIN)External clock input “H” pulse width 37 ns
tWL(XIN)External clock input “L” pulse width 37 ns
tC(CNTR)
CNTR0, CNTR1 input cycle time
(except bi-phase counter mode) 1600 ns
CNTR0 input cycle time (bi-phase counter mode) 2000 ns
tWH(CNTR)
CNTR0, CNTR1 input “H” pulse width
(except bi-phase counter mode) 800 ns
CNTR0 input “H” pulse width (bi-phase counter mode) 1000 ns
tWL(CNTR)
CNTR0, CNTR1 input “L” pulse width
(except bi-phase counter mode) 800 ns
CNTR0 input “L” pulse width (bi-phase counter mode) 1000 ns
tL(CNTR0-TX0)La
g
of CNTR0 and TX0 input ed
g
es
(bi-phase counter mode) 500 ns
tC(TX0)TX
0
input cycle time (bi-phase counter mode) 3200 ns
tWH(TX0)TX
0
input “H” pulse width (bi-phase counter mode) 1600 ns
tWL(TX0)TX
0
input “L” pulse width (bi-phase counter mode) 1600 ns
tWH(INT) INT0, INT1 input “H” pulse width 460 ns
tWL(INT) INT0, INT1 input “L” pulse width 460 ns
tC(SCLK)Serial I/O clock input cycle time 8·t
C
(XIN)ns
tWH(SCLK)Serial I/O clock input “H” pulse width 4·t
C
(XIN)ns
tWL(SCLK)Serial I/O clock input “L” pulse width 4·t
C
(XIN)ns
tSU(SIN–SCLK)Serial I/O input setup time 200 ns
tH(SCLK–SIN)Serial I/O input hold time 150 ns
(VCC=4.0 to 5.5 V, VSS=AVSS=0 V, Ta=–40 to 85 °C unless otherwise noted)
46
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 49 Circuit for measuring output switching characteristics
Table 12: Switching characteristics
Symbol Parameter Limits Unit
min. typ. max.
tWH(SCLK) Serial I/O clock output “H” pulse width 0.5 · tC(SCLK)–50 ns
tWL(SCLK) Serial I/O clock output “L” pulse width 0.5 · tC(SCLK)–50 ns
tD(SCLK–SOUT)Serial I/O output delay time 50 ns
tV(SCLK–SOUT)Serial I/O output valid time 0 50 ns
tR(SCLK)Serial I/O clock output rise time 50 ns
tR(CMOS) CMOS output rise time 10 50 ns
tF(CMOS) CMOS output fall time 10 50 ns
measurement output pin
100 pF
CMOS output
(VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)
MITSUBISHI MICROCOMPUTERS
7630 Group
47
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMING DIAGRAM
Fig. 50 Timing diagram
tWL(INT)tWH(INT)
0.8·VCC 0.2·VCC
tWL(RESET)
0.2·VCC
tWL(XIN)tWH(XIN)
0.8·VCC 0.2·VCC
tC(XIN)
0.8·VCC
0.2·VCC
tWL(SCLK)t
WH(SCLK)
tC(SCLK)
tFtR
0.2·VCC
0.8·VCC
tSU(SIN-SCLK)tH(SCLK-SIN)
tD(SCLK-SOUT)t
V
(SCLK-SOUT)
SOUT
SIN
SCLK
XIN
RESET
INT0, INT1
tWL(CNTR)tWH(CNTR)
0.8·VCC 0.2·VCC
CNTR0, CNTR1
tC(CNTR)
tWL(TX0)tWH(TX0)
0.8·VCC 0.2·VCC
TX0
tC(TX0)
1
Revision Report M37630 E4/M4
REVISION
7630 English Data Sheets
REVISION DATE Page MODIFICATIONS
1.1 10. 98 “CAN controller” is replaced by “CAN module” in whole
document.
11 11 Schematics (8) and (11) are corrected.
18 18 Replaced: “PUPDj” with “PUP4j”
26 26 Replaced: “UTXD” with “SOUT”
Replaced: “URXD” with “SIN”
38 38 Replaced: “FFFBH” with “FFFB16”
Replaced: “FFFAH” with “FFFA16”
41 Replaced: “44P6N” with “44P6N-A)
(1.2) 13.01.99 43 43 Values changed:Iih(35, 113) to (20, 200) and Iil(-122, -70) to
(-200, -20); typical values are removed.
10 10 Schematic (1) is modified.
35 35 Fig. 39 is modified.
New Old