Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
1
Copyright
©
Cirrus Logic, Inc. 2004
(All Rights Reserved)
http://www.cirrus.com
CS42406
24-Bit, 192 kHz 2-In 6-Out Audio CODEC
D/A Features
24-Bit Conversion
102 dB Dynamic Range at 5 V
-91 dB THD+N
Digital Volume Control with Soft Ramp
– 119 dB Attenuation
– 1 dB Step Size
– Zero Crossing Click-Free Transitions
I²C & SPI™ Host Control Port
ATAPI Mixing
Low Clock Jitter Sensitivity
Popguard Technology® for Control of Clicks
and Pops
A/D Features
24-Bit Conversion
105 dB Dynamic Range at 5 V
-98 dB THD+N
Advanced Multi-Bit Delta-Sigma
Architecture
High Pass Filter to Remove DC Offsets
Auto-Mode Selection
System Features
Direct interface with 5 V to 1.8 V logic levels
Supports Independent, Synchronous
ADC/DAC Sample Rates
Operation as Clock Master or Slave
Supports all Audio Sample Rates Including
192 kHz
Single-Ended Inputs/Outputs
Analog/Digital Core Supplies From 3.3 V to
5V
VLC = 1.8 V to 5 V
Mute
Controls
∆Σ
Modulators
Anti-Alias Filter
External
Mute ControlRegister / Hardware
Configuration
Internal Voltage
Reference
Mixers
Interpolation
Filters
PDN/Reset
Switched
Capacitor DACs
and Filters
Multibit
Oversampling
ADC
Multibit
Oversampling
ADC
Anti-Alias Filter
High Pass Filter
High Pass Filter
PCM Serial Interface
Left Input
Right Input
Volume
Controls
Level TranslatorLevel Translator
Serial Audio
Input/Output
VD = 3.3 V to 5 V
Hardware or
I2C/SPI
Control Data
VA = 3.3 V to 5 V
Analog
Outputs
VLS
1.8 V to 5 V
DEC ‘04
DS614PP5
CS42406
2DS614PP5
Stand Alone Mode Feature Set
System features
– ADC serial audio port master or slave
operation
– Independent ADC and DAC reset/power-down
– 256x or 384x MCLK/LRCK ratio selectable
D/A features
– Auto-mute on static samples
– 44.1 kHz 50/15 µs de-emphasis available
– Selectable serial audio interface formats
Left justified up to 24-bit data
I²S up to 24-bit data
Right justified, 16-bit data
Right justified, 24-bit data
A/D features
– Serial audio port master or slave operation
– Auto-mode select in slave mode
– High-pass filter
– Selectable serial audio interface formats
Left justified up to 24-bit
I²S up to 24-bit data
Control Port Mode Feature Set
D/A features
– Selectable auto-mute
– Selectable 32, 44.1, and 48 kHz de-emphasis
filters
– Configurable ATAPI mixing functions
– Configurable volume and muting controls
– Selectable serial audio interface formats
Left justified up to 24-bit
I²S up to 24-bit
Right justified 16, 18, 20, and 24-bit
General Description
The CS42406 is a low cost, integrated audio CO-
DEC. The CS42406 performs stereo analog-to-
digital (A/D) conversion and six channels of digital-
to-analog (D/A) conversion of up to 24-bit serial
values at sample rates up to 200 kHz.
The D/A offers a volume control that operates with
a 1 dB step size. It incorporates selectable soft
ramp and zero crossing transition functions to elim-
inate clicks and pops.
The D/A’s integrated digital mixing functions allow
a variety of output configurations ranging from a
channel swap to a stereo-to-mono down-mix.
Standard 50/15 µs de-emphasis is available for
sampling rates of 32, 44.1, and 48 kHz for compat-
ibility with digital audio programs mastered using
the 50/15 µs pre-emphasis technique.
Integrated level translators allow easy interfacing
between the CS42406 and other devices operating
over a wide range of logic levels.
High-pass filters are available for the right and left
channel of the A/D. This allows the A/D to remove
unwanted DC offsets.
The CS42406’s wide dynamic range, negligible
distortion, and low noise make it ideal for applica-
tions such as A/V receivers, DVD receivers, and
set-top box systems.
ORDERING INFORMATION
CS42406-CQZ -10° to 70° C 48-pin LQFP
CDB42406 Evaluation Board
CS42406
3
TABLE OF CONTENTS
1. PIN DESCRIPTION ................................................................................................................... 6
2 CHARACTERISTICS AND SPECIFICATIONS ......................................................................... 8
SPECIFIED OPERATING CONDITIONS................................................................................. 8
ABSOLUTE MAXIMUM RATINGS ........................................................................................... 8
DAC ANALOG CHARACTERISTICS (CS42406-CQZ)............................................................ 9
DAC FILTER RESPONSE...................................................................................................... 11
ADC ANALOG CHARACTERISTICS (CS42406-CQZ).......................................................... 14
ADC DIGITAL FILTER RESPONSE....................................................................................... 16
DC ELECTRICAL CHARACTERISTICS ................................................................................ 19
DIGITAL CHARACTERISTICS............................................................................................... 20
SWITCHING CHARACTERISTICS - DAC SERIAL AUDIO PORT ........................................ 21
SWITCHING CHARACTERISTICS - ADC SERIAL AUDIO PORT ........................................ 23
SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE....................................... 27
3. TYPICAL CONNECTION DIAGRAM .................................................................................... 29
4. APPLICATIONS ..................................................................................................................... 30
4.1 Single, Double, and Quad-Speed Modes ........................................................................ 30
4.1.1 ADC Serial Port ................................................................................................... 30
4.1.2 DAC Serial Port ................................................................................................... 30
4.1.2a Stand Alone Mode ............................................................................... 30
4.1.2b Control Port Mode ................................................................................ 31
4.2 ADC Serial Port Operation as Either a Clock Master or Slave ........................................ 31
4.2.1 Operation as a Clock Master .............................................................................. 31
4.2.2 Operation as a Clock Slave ................................................................................ 32
4.3 Digital Interface Format ...................................................................................................32
4.3.1 DAC Serial Port ................................................................................................... 32
4.3.1a Stand Alone Mode ............................................................................... 33
4.3.1b Control Port Mode ............................................................................... 33
4.3.2 ADC Serial Port ................................................................................................... 33
4.4 De-Emphasis Control ...................................................................................................... 33
4.4.1 Stand Alone Mode .............................................................................................. 33
4.4.2 Control Port Mode ............................................................................................... 33
4.5 Analog Connections ........................................................................................................ 34
4.5.1 Capacitor Size on the Reference Pin (FILT+) ..................................................... 34
4.6 Recommended Power-up Sequence ............................................................................... 35
4.6.1 Stand Alone Mode .............................................................................................. 35
4.6.2 Control Port Mode ............................................................................................... 35
4.7 Popguard® Transient Control .......................................................................................... 35
4.7.1 Power-up ............................................................................................................. 35
4.7.2 Power-down ........................................................................................................ 35
4.7.3 Discharge Time ................................................................................................... 35
4.8 Mute Control .................................................................................................................... 36
4.9 Grounding and Power Supply Arrangements .................................................................. 36
4.9.1 Capacitor Placement ........................................................................................... 36
4.10 Control Port Interface ....................................................................................................36
4.10.1 Memory Address Pointer (MAP) ....................................................................... 36
4.10.1a INCR (Auto Map Increment) .............................................................. 37
4.10.1b MAP0-3 (Memory Address Pointer) ................................................... 37
4.10.2 I²C Mode ........................................................................................................... 37
4.10.2a I²C Write ............................................................................................. 37
4.10.2b I²C Read ............................................................................................. 37
CS42406
4DS614PP5
4.10.3 SPI Mode .......................................................................................................... 38
4.10.3a SPI Write ............................................................................................ 38
5. REGISTER QUICK REFERENCE ......................................................................................... 40
6. REGISTER DESCRIPTIONS .................................................................................................. 41
6.1 Mode Control 1 (address 01h) ......................................................................................... 41
6.2 Invert Signal (address 02h).............................................................................................. 42
6.3 Mixing Control Pair 1 (Channels A1 & B1) (address 03h)
Mixing Control Pair 2 (Channels A2 & B2) (address 04h)
Mixing Control Pair 3 (Channels A3 & B3) (address 05h)............................................. 42
6.4 Volume Control (addresses 06h - 0Bh) ............................................................................ 44
6.5 Mode Control 2 (address 0Ch).......................................................................................... 44
7 PARAMETER DEFINITIONS ................................................................................................... 47
8. PACKAGE DIMENSIONS ....................................................................................................... 48
9. REVISION HISTORY .............................................................................................................. 49
LIST OF FIGURES
Figure 1. Output Test Load ......................................................................................................... 10
Figure 2. Maximum Loading ........................................................................................................ 10
Figure 3. Single-Speed Stopband Rejection ............................................................................... 12
Figure 4. Single-Speed Transition Band ..................................................................................... 12
Figure 5. Single-Speed Transition Band (Detail) ......................................................................... 12
Figure 6. Single-Speed Passband Ripple ................................................................................... 12
Figure 7. Double-Speed Stopband Rejection .............................................................................. 12
Figure 8. Double-Speed Transition Band .................................................................................... 12
Figure 9. Double-Speed Transition Band (Detail) ....................................................................... 12
Figure 10. Double-Speed Passband Ripple .................................................................................. 12
Figure 11. Single-Speed Mode Stopband Rejection ..................................................................... 16
Figure 12. Single-Speed Mode Stopband Rejection ..................................................................... 16
Figure 13. Single-Speed Mode Transition Band (Detail) ............................................................... 16
Figure 14. Single-Speed Mode Passband Ripple ......................................................................... 16
Figure 15. Double-Speed Mode Stopband Rejection .................................................................... 16
Figure 16. Double-Speed Mode Stopband Rejection .................................................................... 16
Figure 17. Double-Speed Mode Transition Band (Detail) ............................................................. 17
Figure 18. Double-Speed Mode Passband Ripple ........................................................................ 17
Figure 19. Quad-Speed Mode Stopband Rejection ...................................................................... 17
Figure 20. Quad-Speed Mode Stopband Rejection ...................................................................... 17
Figure 21. Quad-Speed Mode Transition Band (Detail) ................................................................ 17
Figure 22. Quad-Speed Mode Passband Ripple ........................................................................... 17
Figure 23. DAC Serial Audio Port .................................................................................................. 21
Figure 24. Master Mode, Left Justified SAI ................................................................................... 24
Figure 25. Slave Mode, Left Justified SAI ..................................................................................... 24
Figure 26. Master Mode, I²S SAI ................................................................................................... 24
Figure 27. Slave Mode, I²S SAI ..................................................................................................... 24
Figure 28. Left Justified up to 24-Bit Data .....................................................................................25
Figure 29. I²S, up to 24-Bit Data .................................................................................................... 25
Figure 30. Right Justified Data ...................................................................................................... 25
Figure 31. Control Port Timing - I²C Mode .................................................................................... 26
Figure 32. Control Port Timing - SPI Mode ................................................................................... 27
Figure 33. Typical Connection Diagram ........................................................................................ 28
CS42406
5
Figure 34. ADC Serial Port, Master Mode Clocking ...................................................................... 31
Figure 35. De-Emphasis Curve ..................................................................................................... 32
Figure 36. CS42406 Recommended Analog Input Buffer ............................................................. 33
Figure 37. CS42406 ADC: THD+N versus Frequency .................................................................. 33
Figure 38. I²C Write ....................................................................................................................... 36
Figure 39. I²C Read ....................................................................................................................... 37
Figure 40. SPI Write ...................................................................................................................... 37
Figure 41. ATAPI Block Diagram ..................................................................................................41
LIST OF TABLES
Table 1. ADC Speed Modes and the Associated Output Sample Rates (Fs) for 256x Mode .......... 29
Table 2. ADC Speed Modes and the Associated Output Sample Rates (Fs) for 384x Mode .......... 29
Table 3. CS42406 Stand Alone DAC Operational Modes................................................................ 30
Table 4. CS42406 Control Port DAC Operational Modes ................................................................ 30
Table 5. CS42406 ADC Serial Port Mode Control ........................................................................... 30
Table 6. DAC Digital Interface Format - Stand Alone Mode............................................................. 32
Table 7. Digital Interface Formats - Control Port Mode.................................................................... 39
Table 8. ATAPI Decode.................................................................................................................... 41
Table 9. Example Digital Volume Settings ....................................................................................... 42
Table 10. Revision History ............................................................................................................... 47
CS42406
6DS614PP5
1. PIN DESCRIPTION
Pin Name #Pin Description
DAC_SCLK 1DAC Serial Clock (
Input
) - Serial clock for the DAC serial audio interface.
DAC_LRCK 2DAC Left Right Clock (
Input
) - Determines which channel, Left or Right, is currently active on the
DAC serial audio data line.
MCLK 3Master Clock (
Input
) - Clock source for the delta-sigma modulators and digital filters.
VLS 4
45
Serial Audio Interface Power (
Input
) - Positive power for the serial audio interface.
SDOUT 5Serial Audio Data Output
(Output)
- Output for two’s complement serial audio data.
ADC_384x/256x 6ADC MCLK/LRCK Ratio Select
(Input)
- Selects the base MCLK/LRCK ratio for the ADC serial
port.
VD 7
9
Digital Power (
Input
) - Positive power supply for the digital section.
GND 8
31
33
Ground (
Input
)
RST_DAC 10 DAC Reset (
Input
) - Powers down the DAC and resets all internal resisters to their default settings.
ADC_SCLK 11 ADC Serial Clock (
Input/Output
) - Serial clock for the ADC serial audio interface.
ADC_LRCK 12 ADC Left Right Clock (
Input/Output
) - Determines which channel, Left or Right, is currently active
on the ADC serial audio data line.
VLC 16 Control Port Interface Power (
Input
) - Positive power for the control port interface.
ADC_PDN 18 ADC Power-Down
(Input)
- The ADC enters a low power mode when low.
TST 19,20
23,27
35,42
Test Pin
(Input)
- Connect to GND.
DIF1/SCL/CCLK
GND
GND
AOUTB3
TST
ADC_FILT+
VA
AOUTA3
MUTEC3
6
2
4
8
10
1
3
5
7
9
11
12
13 14 15 16 17 18 19 20 21 22 23 24
31
35
33
29
27
36
34
32
30
28
26
25
48 47 46 45 44 43 42 41 40 39 38 37
ADC_384x/256x
DAC_LRCK
VLS
GND
DAC_RST
DAC_SCLK
MCLK
SDOUT
VD
ADC_SCLK
ADC_LRCK
VD
ADC_M0
SDIN3
TST
SDIN2
CS42406
SDIN1
VLS
DIF0/SDA/CDIN
DAC_M0/AD0/CS
VLC
ADC_PDN
TST
TST
DAC_FILT+
DAC_VQ
DAC_M1
TST
AOUTB2
MUTEC2
AOUTA2
AOUTA1
AOUTB1
MUTEC1
ADC_M1
AINR
ADC_VQ
AINL
TST
CS42406
7
DAC_FILT+ 21 Positive Voltage Reference (
Output
) - Positive reference voltage for the internal sampling circuits.
DAC_VQ 22 Quiescent Voltage (
Output
) - Filter connection for internal quiescent voltage.
AINL
AINR
24
26
Analog Inputs
(Input)
- The full scale analog input level is specified in the “ADC Analog Character-
istics (CS42406-CQZ)” on page 14.
ADC_VQ 25 Quiescent Voltage (
Output
) - Filter connection for internal quiescent voltage.
AOUTB3
AOUTA3
AOUTB2
AOUTA2
AOUTB1
AOUTA1
29
30
36
37
39
40
Analog Outputs (
Output
) - The full scale analog line output level is specified in the “DAC Analog
Characteristics (CS42406-CQZ)” on page 9.
MUTEC3
MUTEC2
MUTEC1
28
38
41
Mute Control (
Output
) - Control signals for optional mute circuit.
VA 32 Analog Power (
Input
) - Positive power supply for the analog section.
ADC_FILT+ 34 Positive Voltage Reference (
Output
) - Positive reference voltage for the internal sampling circuits.
ADC_M1
ADC_M0
43
44
ADC Mode Selection (
Input
) - Determines the operational speed mode of the ADC.
SDIN1
SDIN2
SDIN3
46
47
48
Serial Audio Data Input (
Input
) - Input for two’s complement serial audio data.
DAC Control
Port Definitions
SCL/CCLK 13 Serial Control Port Clock (
Input
) - Serial clock for the control port interface.
SDA/CDIN 14 Serial Control Data I/O (
Input/Output
) - Input/Output for I²C data. Input for SPI data.
AD0/CS 15 Address Bit / Chip Select (
Input
) - Chip address bit in I²C Mode. Control signal used to select the
chip in SPI mode.
DAC Stand
Alone Defini-
tions
DIF1
DIF0
13
14
Digital Interface Format (
Input
) - Defines the required relationship between the Left Right Clock,
Serial Clock and Serial Audio Data for the DAC.
DAC_M0
DAC_M1
15
17
Mode Selection (
Input
) - Determines the operational speed mode of the DAC.
CS42406
8DS614PP5
2 CHARACTERISTICS AND SPECIFICATIONS
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical
performance characteristics and specifications are derived from measurements taken at typical supply voltages
and TA = 25°C.)
SPECIFIED OPERATING CONDITIONS
(GND = 0 V, all voltages with respect to 0 V.)
Notes: 1. This part is specified at typical analog voltages of 3.3 V and 5.0 V. See
DAC Analog Characteristics
(CS42406-CQZ)
and
ADC Analog Characteristics (CS42406-CQZ)
for details.
2. Nominal VD supply must be less than or equal to the nominal VA supply.
3. In 384x Mode for the ADC, Quad-Speed Slave Mode operation is limited to a nominal VA and VD of 5 V.
4. In 384x Mode for the ADC, Double-Speed & Quad-Speed Mode operation is limited to a minimum VL of
2.5 V
ABSOLUTE MAXIMUM RATINGS
(GND = 0 V, All voltages with respect to ground.) (Note 7)
Notes: 5. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause SRC
latch-up.
6. The maximum over/under voltage is limited by the input current.
7. Operation beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
Parameter Symbol Min Typ Max Unit
Power Supplies Analog (Note 3)
Digital (Note 2, 3)
Logic/Serial Interface (Note 4)
Control Port Interface
VA
VD
VLS
VLC
3.1
3.1
1.7
1.7
(Note 1)
3.3
3.3
3.3
5.25
5.25
5.25
5.25
V
V
V
V
Ambient Temperature
Commercial -CQZ TA-10 - +70 °C
Parameter Symbol Min Max Units
DC Power Supplies: Analog
Digital
Serial Audio Interface (SAI)
Control Port Interface
VA
VD
VLS
VLC
-0.3
-0.3
-0.3
-0.3
+6.0
+6.0
+6.0
+6.0
V
V
V
V
Input Current (Note 5) Iin -±10 mA
Analog Input Voltage (Note 6) VIN GND-0.7 VA+0.7 V
Digital Input Voltage(Note 6) Serial Audio Data Interface
Control Port Interface
VIND_S
VIND_S
-0.3
-0.3
VLS+0.4
VLC+0.4
V
V
Ambient Operating Temperature (Power Applied) TA-50 +95 °C
Storage Temperature Tstg -65 +150 °C
CS42406
9
DAC ANALOG CHARACTERISTICS (CS42406-CQZ) Test conditions (unless otherwise
specified): Input test signal is a 997 Hz sine wave at 0 dBFS; measurement bandwidth is 10 Hz to 20 kHz; test load
RL = 10 kΩ, CL = 10 pF (see Figure 1).
Notes: 8. One-half LSB of triangular PDF dither is added to data.
Parameter
VA = 5.0 V VA = 3.3 V
Min Typ Max Min Typ Max Unit
Single-Speed Mode Fs = 48 kHz
Dynamic Range (Note 8)
unweighted
A-Weighted
93
96
99
102
-
-
88
91
94
97
-
-
dB
dB
Total Harmonic Distortion + Noise (Note 8)
0 dB
-20 dB
-60 dB
-
-
-
-91
-79
-39
-85
-
-
-
-
-
-91
-74
-34
-85
-
-
dB
dB
dB
Double-Speed Mode Fs = 96 kHz
Dynamic Range (Note 8)
unweighted
A-Weighted
40 kHz Bandwidth A-Weighted
93
96
-
99
102
100
-
-
-
88
91
-
94
97
97
-
-
-
dB
dB
dB
Total Harmonic Distortion + Noise (Note 8)
0 dB
-20 dB
-60 dB
-
-
-
-91
-79
-39
-85
-
-
-
-
-
-91
-74
-34
-85
-
-
dB
dB
dB
Quad-Speed Mode Fs = 192 kHz
Dynamic Range (Note 8)
unweighted
A-Weighted
40 kHz Bandwidth A-Weighted
93
96
-
99
102
100
-
-
-
88
91
-
94
97
97
-
-
-
dB
dB
dB
Total Harmonic Distortion + Noise (Note 8)
0 dB
-20 dB
-60 dB
-
-
-
-91
-79
-39
-85
-
-
-
-
-
-91
-74
-34
-85
-
-
dB
dB
dB
CS42406
10 DS614PP5
DAC ANALOG CHARACTERISTICS (CS42406-CQZ) (Continued)
9. See Figure 1-2. RL and CL reflect the recommended minimum resistance and maximum capacitance
required for the internal op-amp's stability and signal integrity. In this circuit topology, CL will effectively
move the dominant pole of the two-pole amp in the output stage. Increasing this value beyond the
recommended 100 pF can cause the internal op-amp to become unstable.
.
Parameters Symbol Min Typ Max Units
Dynamic Performance for All Modes
Interchannel Isolation (1 kHz) - 102 - dB
DC Accuracy
Interchannel Gain Mismatch ICGM - 0.1 - dB
Gain Drift - ±100 - ppm/°C
Analog Output Characteristics and Specifications
Full Scale Output Voltage 0.60•VA 0.66•VA 0.72•VA Vpp
Output Impedance Zout - 100 - Ω
Minimum AC-Load Resistance (Note 7) RL-3-kΩ
Maximum Load Capacitance (Note 7) CL- 100 - pF
AOUTx
AGND
3.3 µF
V
out
RLCL
+
Figure 1. Output Test Load
100
50
75
25
2.5
51015
Safe Operating
Region
Capacitive Load -- C (pF)
L
Resistive Load -- R (k
Ω
)
L
125
3
20
Figure 2. Maximum Loading
CS42406
11
DAC FILTER RESPONSE The filter characteristics and the X-axis of the response plots have been nor-
malized to the input sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given char-
acteristic by Fs.
Notes: 10. For Single-Speed Mode, the measurement bandwidth is 0.5465 Fs to 3 Fs.
For Double-Speed Mode, the measurement bandwidth is 0.577 Fs to 1.4 Fs.
11. De-emphasis is only available in Single-Speed Mode.
Parameter Min Typ Max Unit
Single-Speed Mode - (4 kHz to 50 kHz sample rates)
Passband
to -0.05 dB corner
to -3 dB corner
0
0
-
-
0.4535
0.4998
Fs
Fs
Passband Ripple -0.02 - +0.035 dB
StopBand 0.5465 - - Fs
StopBand Attenuation (Note 10) 50 - - dB
Group Delay - 9/Fs - s
De-emphasis Error (Relative to 1 kHz) (Note 11)
Control Port Mode
Fs = 32 kHz
Fs = 44.1 kHz
Fs = 48 kHz
Stand-Alone Mode
Fs = 32 kHz
Fs = 44.1 kHz
Fs = 48 kHz
-
-
-
-
-
-
-
-
-
-
-
-
+0.2/-0.1
+0.05/-0.14
+0/-0.22
+1.5/-0
+0.05/-0.14
+0.2/-0.4
dB
dB
dB
dB
dB
dB
Double-Speed Mode - (50 kHz to 100 kHz sample rates)
Passband
to -0.1 dB corner
to -3 dB corner
0
0
-
-
0.4621
0.4982
Fs
Fs
Passband Ripple -0.1 - 0 dB
StopBand 0.577 - - Fs
StopBand Attenuation (Note 10) 55 - - dB
Group Delay - 4/Fs - s
Quad-Speed Mode - (100 kHz to 200 kHz sample rates)
Passband
to -3 dB corner 0 - 0.25 Fs
Passband Ripple -0.7 - 0 dB
Group Delay - 1.5/Fs - s
CS42406
12 DS614PP5
Figure 3. Single-Speed Stopband Rejection Figure 4. Single-Speed Transition Band
Figure 5. Single-Speed Transition Band (Detail) Figure 6. Single-Speed Passband Ripple
Figure 7. Double-Speed Stopband Rejection Figure 8. Double-Speed Transition Band
CS42406
13
Figure 9. Double-Speed Transition Band (Detail) Figure 10. Double-Speed Passband Ripple
CS42406
14 DS614PP5
ADC ANALOG CHARACTERISTICS (CS42406-CQZ) Test conditions (unless otherwise
specified): Input test signal is a 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz.
Note: 12. Referred to the typical full-scale input voltage
Parameter
VA = 5.0 V VA = 3.3 V
Min Typ Max Min Typ Max Unit
Single-Speed Mode Fs = 48 kHz
Dynamic Range unweighted
A-Weighted
96
99
102
105
-
-
93
96
99
102
-
-
dB
dB
Total Harmonic Distortion + Noise (Note 12)
-1 dB
-20 dB
-60 dB
-
-
-
-98
-82
-42
-92
-
-
-
-
-
-95
-79
-39
-89
-
-
dB
dB
dB
Double-Speed Mode Fs = 96 kHz
Dynamic Range unweighted
A-Weighted
40 kHz Bandwidth unweighted
96
99
-
102
105
99
-
-
-
93
96
-
99
102
96
-
-
-
dB
dB
dB
Total Harmonic Distortion + Noise (Note 12)
-1 dB
-20 dB
-60 dB
-
-
-
-98
-82
-42
-92
-
-
-
-
-
-95
-79
-39
-89
-
-
dB
dB
dB
Quad-Speed Mode Fs = 192 kHz
Dynamic Range unweighted
A-Weighted
40 kHz Bandwidth unweighted
96
99
-
102
105
99
-
-
-
93
96
-
99
102
96
-
-
-
dB
dB
dB
Total Harmonic Distortion + Noise (Note 12)
-1 dB
-20 dB
-60 dB
-
-
-
-98
-82
-42
-92
-
-
-
-
-
-95
-79
-39
-89
-
-
dB
dB
dB
CS42406
15
ADC ANALOG CHARACTERISTICS (CS42406-CQZ) (Continued)
Parameters Min Typ Max Units
Dynamic Performance for All Modes
Interchannel Isolation - 90 - dB
DC Accuracy
Interchannel Gain Mismatch - 0.1 - dB
Gain Error - - ±10 %
Gain Drift - ±100 - ppm/°C
Analog Input Characteristics
Full Scale Input Voltage 0.53•VA 0.56•VA 0.59•VA Vpp
Input Impedance 18 - - kΩ
CS42406
16 DS614PP5
ADC DIGITAL FILTER RESPONSE The filter characteristics and the X-axis of the response plots
have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the
given characteristic by Fs.
Note: 13. Response shown is for Fs equal to 48 kHz.
Parameter Min Typ Max Unit
Single-Speed Mode (4 kHz to 50 kHz sample rates)
Passband to -0.1 dB corner 0 - 0.49 Fs
Passband Ripple - - 0.035 dB
Stopband 0.57 - - Fs
Stopband Attenuation 70 - - dB
Total Group Delay - 12/Fs - s
Double-Speed Mode (50 kHz to 100 kHz sample rates)
Passband to -0.1 dB corner 0 - 0.49 Fs
Passband Ripple - - 0.025 dB
Stopband 0.56 - - Fs
Stopband Attenuation 69 - - dB
Total Group Delay - 9/Fs - s
Quad-Speed Mode (100 kHz to 200 kHz sample rates)
Passband to -0.1 dB corner 0 - 0.26 Fs
Passband Ripple - - 0.025 dB
Stopband 0.50 - - Fs
Stopband Attenuation 60 - - dB
Total Group Delay - 5/Fs - s
High Pass Filter Characteristics
Frequency Response -3.0 dB
-0.13 dB (Note 13)
-1
20
-
-
Hz
Hz
Phase Deviation @ 20 Hz (Note 13) - 10 - Deg
Passband Ripple - - 0 dB
CS42406
17
Figure 11. Single-Speed Mode Stopband Rejection Figure 12. Single-Speed Mode Stopband Rejection
Figure 13. Single-Speed Mode Transition Band (Detail) Figure 14. Single-Speed Mode Passband Ripple
Figure 15. Double-Speed Mode Stopband Rejection Figure 16. Double-Speed Mode Stopband Rejection
-140
-130
-120
- 110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0 .0 0 .1 0 .2 0 .3 0 .4 0 .5 0 .6 0 .7 0 .8 0 .9 1.0
Frequency (normalized to Fs)
Amplitude (dB)
-140
-130
-120
- 110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60
Frequency (normalized to Fs)
Amplitude (dB)
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55
Frequency (normalized to Fs)
Amplitude (dB)
-0.10
-0.08
-0.06
-0.04
-0.02
0.00
0.02
0.04
0.06
0.08
0.10
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Frequency (norm alized to Fs)
Amplitude (dB)
-140
-130
-120
- 110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0 .0 0 .1 0 .2 0 .3 0 .4 0 .5 0 .6 0 .7 0 .8 0 .9 1.0
Frequency (normalized to Fs)
Amplitude (dB)
-140
-130
-120
- 110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60
Frequency (normalized to Fs)
Amplitude (dB)
CS42406
18 DS614PP5
Figure 17. Double-Speed Mode Transition Band (Detail) Figure 18. Double-Speed Mode Passband Ripple
Figure 19. Quad-Speed Mode Stopband Rejection Figure 20. Quad-Speed Mode Stopband Rejection
Figure 21. Quad-Speed Mode Transition Band (Detail) Figure 22. Quad-Speed Mode Passband Ripple
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
0.46 0.47 0.48 0.49 0.50 0.51 0.52
Frequency (normalized to Fs)
Amplitude (dB)
-0.10
-0.08
-0.06
-0.04
-0.02
0.00
0.02
0.04
0.06
0.08
0.10
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Frequency (norm alized to Fs)
Amplitude (dB)
-140
-130
-120
- 110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0 .0 0 .1 0 .2 0 .3 0 .4 0 .5 0 .6 0 .7 0 .8 0 .9 1.0
Frequency (normalized to Fs)
Amplitude (dB)
-140
-130
-120
- 110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85
Frequency (normalized to Fs)
Amplitude (dB)
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Frequency (normalized to Fs)
Amplitude (dB)
-0.10
-0.08
-0.06
-0.04
-0.02
0.00
0.02
0.04
0.06
0.08
0.10
0.00 0.03 0.05 0.08 0.10 0.13 0.15 0.18 0.20 0.23 0.25 0.28
Frequency (normalized to Fs)
Amplitude (dB)
CS42406
19
DC ELECTRICAL CHARACTERISTICS GND = 0 V; all voltages with respect to GND.
Notes: 14. Normal operation is defined as RST = HI with a 997 Hz, 0 dBFS digital input sampled at the highest Fs
for each speed mode, and open outputs, unless otherwise specified. Analog inputs are driven with a 1
kHz, -1 dBFS sine wave and sampled at the highest Fs for each speed mode.
15. IDT measured with no external loading on pin 14 (SDA).
16. Power Down Mode is defined as DAC_RST = LO, PDN_ADC = LO, with all clocks and data lines held
static.
17. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figure 33.
Parameters Symbol Min Typ Max Units
Normal Operation
(Note 14)
Power Supply Current VA = 5.0 V
VD, VLS, VLC = 5.0 V
VA = 3.3 V
VD, VLS, VLC = 3.3 V
(Note 15)
IA
IDT
IA
IDT
-
-
-
-
43
40
40
25
48
45
44
26
mA
mA
mA
mA
Power Dissipation All Supplies = 5.0 V
All Supplies = 3.3 V
-
-
415
215
465
231
mW
mW
Power-down Mode
(Note 16)
Power Supply Current All Supplies = 5.0 V
All Supplies = 3.3 V
-
-
2
1
-
-
mA
mA
Power Dissipation All Supplies = 5.0 V
All Supplies = 3.3 V
-
-
10
3.3
-
-
mW
mW
All Modes of Operation
Power Supply Rejection Ratio (Note 17) 1 kHz PSRR - 60 - dB
VQ Nominal Voltage
Output Impedance DAC_VQ
ADC_VQ
Maximum allowable DC current source/sink
-
-
-
-
0.5•VA
250
25
0.01
-
-
-
-
V
kΩ
kΩ
mA
Filt+ Nominal Voltage - VA - V
MUTEC Low-Level Output Voltage - 0 - V
MUTEC High-Level Output Voltage - VA - V
Maximum MUTEC Drive Current - 3 - mA
CS42406
20 DS614PP5
DIGITAL CHARACTERISTICS GND = 0 V; all voltages with respect to GND.
Parameters Symbol Min Typ Max Units
Input Leakage Current Iin --±10µA
Input Capacitance - 8 - pF
High-Level Input Voltage (% of VLS/VLC) VIH 70% - - V
Low-Level Input Voltage (% of VLS/VLC) VIL --13%V
High-Level Output Voltage at Io = 100 µA (% of VLS/VLC) VOH 70% - - V
Low-Level Output Voltage at Io =100 µA (% of VLS/VLC) VOL --15%V
CS42406
21
SWITCHING CHARACTERISTICS - DAC SERIAL AUDIO PORT (Logic “0” = GND =
0 V, Logic “1” = VLS)
* For a description of Speed Modes, please refer to Section 4.1.2 on page 30.
Parameter Symbol Min Typ Max Unit
MCLK Specifications
MCLK Frequency 1.024 - 12.8 MHz
22 - 25.6 MHz
MCLK Duty Cycle 45 - 55 %
Single-Speed*
DAC_LRCK Duty Cycle 45 - 55 %
DAC_SCLK Frequency - - 128×Fs Hz
DAC_SCLK Pulse Width Low tsclkl 20 - - ns
DAC_SCLK Pulse Width High tsclkh 20 - - ns
DAC_SCLK rising to DAC_LRCK edge delay tslrd 20 ns
DAC_SCLK rising to DAC_LRCK edge setup time tslrs 20 ns
SDINx valid to DAC_SCLK rising setup time tsdlrs 20 ns
DAC_SCLK rising to SDINx hold time tsdh 20 ns
Double-Speed*
DAC_LRCK Duty Cycle 45 - 55 %
DAC_SCLK Frequency - - 64×Fs Hz
DAC_SCLK Pulse Width Low tsclkl 20 - - ns
DAC_SCLK Pulse Width High tsclkh 20 - - ns
DAC_SCLK rising to DAC_LRCK edge delay tslrd 20 ns
DAC_SCLK rising to DAC_LRCK edge setup time tslrs 20 ns
SDINx valid to DAC_SCLK rising setup time tsdlrs 20 ns
DAC_SCLK rising to SDINx hold time tsdh 20 ns
Quad-Speed*
DAC_LRCK Duty Cycle 45 - 55 %
DAC_SCLK Frequency - - MCLK/2 Hz
DAC_SCLK Pulse Width Low tsclkl 20 - - ns
DAC_SCLK Pulse Width High tsclkh 20 - - ns
DAC_SCLK rising to DAC_LRCK edge delay tslrd 20 ns
DAC_SCLK rising to DAC_LRCK edge setup time tslrs 20 ns
SDINx valid to DAC_SCLK rising setup time tsdlrs 20 ns
DAC_SCLK rising to SDINx hold time tsdh 20 ns
CS42406
22 DS614PP5
Figure 23. DAC Serial Audio Port
sclkh
t
slrs
t
slrd
t
sdlrs
tsdh
t
sclkl
t
SDINx
DAC_SCLK
DAC_LRCK
CS42406
23
SWITCHING CHARACTERISTICS - ADC SERIAL AUDIO PORT Logic “0” = GND =
0 V; Logic “1” = VLS, CL = 20 pF.
NOTE: Certain parameters depend on the 256x/384x (pin6) mode setting and are separated below.
Parameter Symbol Min Typ Max Unit
MCLK Duty Cycle 45 - 55 %
Master Mode
ADC_SCLK falling to ADC_LRCK tmslr -20 - 20 ns
ADC_SCLK falling to SDOUT valid tsdo 0 - 32 ns
Slave Mode
Single-Speed*
ADC_LRCK Frequency MCLK = 256, 384 Fs (÷1 or 1.5)
(Note 18) MCLK = 512, 768 Fs (÷2 or 3)
Fs
Fs
4
43
-50
50
kHz
kHz
ADC_LRCK Duty Cycle 40 - 60 %
SDOUT valid before ADC_SCLK rising tstp 10 - - ns
SDOUT valid after ADC_SCLK rising thld 5--ns
ADC_SCLK falling to ADC_LRCK edge tslrd -20 - 20 ns
Double-Speed*
ADC_LRCK Frequency MCLK = 128, 192 Fs (÷1 or 1.5)
(Note 18) MCLK = 256, 384 Fs (÷2 or 3)
Fs
Fs
50
86
-100
100
kHz
kHz
ADC_LRCK Duty Cycle 40 - 60 %
SDOUT valid before ADC_SCLK rising tstp 10 - - ns
SDOUT valid after ADC_SCLK rising thld 5--ns
ADC_SCLK falling to ADC_LRCK edge tslrd -20 - 20 ns
Quad-Speed*
ADC_LRCK Frequency
(Note 18) MCLK = 128 Fs (÷2 or 3) Fs 172 - 200 kHz
ADC_LRCK Duty Cycle 40 - 60 %
SDOUT valid before ADC_SCLK rising tstp 10 - - ns
SDOUT valid after ADC_SCLK rising thld 5--ns
ADC_SCLK falling to ADC_LRCK edge tslrd -8 - 8 ns
CS42406
24 DS614PP5
* For a description of Speed Modes, please refer to Table 1 on page 30.
18. Internal ÷ is automatically determined when operating within the specified limits.
256x Mode
(pin 6 = LO)
MCLK Frequency (Note 18) Internal ÷1 1.024 - 12.8 MHz
Internal ÷2 22.016 - 25.6 MHz
Master Mode
ADC_SCLK Duty Cycle Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
-
-
-
50
50
50
-
-
-
%
%
%
ADC_LRCK Frequency (Note 18)
MCLK = 64 Fs (÷1) Quad-Speed Mode Fs 100 - 200 kHz
Slave Mode
ADC_SCLK Period Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
tsclkw 156
156
78
-
-
-
-
-
-
ns
ns
ns
ADC_SCLK Duty Cycle Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
45
45
45
-
-
-
55
55
55
%
%
%
384x Mode
(pin 6 = HI)
MCLK Frequency (Note 18) Internal ÷1.5 1.536 - 19.2 MHz
Internal ÷3 33.024 - 38.4 MHz
Master Mode
ADC_SCLK Duty Cycle Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
-
-
-
50
50
33
-
-
-
%
%
%
ADC_LRCK Frequency (Note 18)
MCLK = 96 Fs (÷1.5) Quad-Speed Mode Fs 100 - 200 kHz
Slave Mode
ADC_SCLK Period Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
tsclkw 290
193
104
-
-
-
-
-
-
ns
ns
ns
ADC_SCLK Duty Cycle Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
45
45
45
-
-
-
55
55
50
%
%
%
CS42406
25
LRCK input
SCLK input
SDOUT MSB
tstp thld
tsclkw
MSB-1
tslrd
SCLK output
SDOUT
LRCK output
MSB MSB-1
tsdo
tmslr
Figure 24. Master Mode, Left Justified SAI Figure 25. Slave Mode, Left Justified SAI
SCLK output
SDOUT
LRCK output
MSB
tmslr
MSB-1
tsdo
LRCK input
SCLK input
SDOUT
tstp thld
tsclkw
MSB
tslrd
Figure 26. Master Mode, I²S SAI Figure 27. Slave Mode, I²S SAI
CS42406
26 DS614PP5
ADC/DAC_LRCK
ADC/DAC_SCLK
MSB LSB MSB LSB
AOUTAx
Left Channel Right Channel
SDOUT
SDINx
AOUTBx
MSB
AINl AINR
Figure 28. Left Justified up to 24-Bit Data
ADC/DAC_LRCK
ADC/DAC_SCLK
MSB LSB MSB LSB
AOUTAx
Left Channel Right Channel
SDOUTx
SDINx
AOUTBx
MSB
AINL AINR
Figure 29. I²S, up to 24-Bit Data
ADC/DAC_LRCK
ADC/DAC_SCLK
MSB LSB MSB LSB
AOUTAx
Left Channel Right Channel
SDINx
AOUTBx
Figure 30. Right Justified Data
CS42406
27
SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE Inputs: Logic
0 = GND, Logic 1 = VLC
Notes: 19. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
20. The acknowledge delay is based on MCLK and can limit the maximum transaction speed.
21. for Single-Speed Mode, for Double-Speed Mode, for Quad-Speed Mode.
Parameter Symbol Min Max Unit
I²C Mode
SCL Clock Frequency fscl - 100 kHz
DAC_RST Rising Edge to Start tirs 500 - ns
Bus Free Time Between Transmissions tbuf 4.7 - µs
Start Condition Hold Time (prior to first clock pulse) thdst 4.0 - µs
Clock Low time tlow 4.7 - µs
Clock High Time thigh 4.0 - µs
Setup Time for Repeated Start Condition tsust 4.7 - µs
SDA Hold Time from SCL Falling (Note 19) thdd 0-µs
SDA Setup time to SCL Rising tsud 250 - ns
Rise Time of SCL and SDA trc, trc -1µs
Fall Time SCL and SDA tfc, tfc - 300 ns
Setup Time for Stop Condition tsusp 4.7 - µs
Acknowledge Delay from SCL Falling (Note 20) tack - (Note 21) ns
5
2
56 Fs×
---------- ---- ---- -----
5
128 Fs
×
-
--------- ---- ---- -----5
64 Fs
×
--------------------
tbuf thdst
tlow thdd
thigh
tsud
Stop St a rt
SDA
SCL
tirs
thdst
trc
tfc
tsust
tsusp
Start Stop
Repeated
trd tfd
tack
DAC_RST
Figure 31. Control Port Timing - I²C Mode
CS42406
28 DS614PP5
SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE (Continued)
Notes: 22. tspi only needed before first falling edge of CS after DAC_RST rising edge. tspi = 0 at all other times.
23. Data must be held for sufficient time to bridge the transition time of CCLK.
24. For fsclk < 1 MHz.
Parameter Symbol Min Max Unit
SPI Mode
CCLK Clock Frequency fsclk -6MHz
DAC_RST Rising Edge to CS Falling tsrs 500 - ns
CCLK Edge to CS Falling (Note 22) tspi 500 - ns
CS High Time Between Transmissions tcsh 1.0 - µs
CS Falling to CCLK Edge tcss 20 - ns
CCLK Low Time tscl -ns
CCLK High Time tsch -ns
CDIN to CCLK Rising Setup Time tdsu 40 - ns
CCLK Rising to DATA Hold Time (Note 23) tdh 15 - ns
Rise Time of CCLK and CDIN (Note 24) tr2 - 100 ns
Fall Time of CCLK and CDIN (Note 24) tf2 - 100 ns
1
MCLK
-----------------
1
MCLK
-----------------
tr2 tf2
tdsu tdh
tsch
tscl
CS
CCLK
CDIN
tcss tcsh
tspi
tsrs
DAC_RST
Figure 32. Control Port Timing - SPI Mode
CS42406
29
3. TYPICAL CONNECTION DIAGRAM
33
VLS
GND
CS42406
MCLK
VA
AOUTA1
1
46
47
7,9
0.01 µF 1 µF
+3.3 V to +5 V
15
10
14
SDIN1
2
DIF1/SCL/CCLK
DIF0/SDA/CDIN
DAC_M0/AD0/CS
DAC_RST
MUTEC1
OPTIONAL
MUTE
CIRCUIT
3.3 µF 0.01 µF
AOUTA1
C = 4πFs(R 560)
RL
+
+
21
22
DAC_FILT+
DAC_VQ
13
17 DAC_M1
3
DAC_LR CK
DAC_SCLK
SDIN 3
SDIN 2
3.3 µF 10 k ΩC
560 Ω
+
41
40
3.3 µF C
560 Ω
+
39 AOUTB1
RL
560 Ω
OPTIONAL
MUTE
CIRCUIT
AOUTA3
R
3.3 µF 10 k ΩC
560 Ω
+
28
30
3.3 µF 10 k ΩC
560 Ω
+
29 AOUTB3
RLOAD
AOUTB1
0.01 µF 3.3 µF
AOUTA3
MUTEC 3
AOUTB3
VD
0.01 µF
1 µF
GND
8
0.01 µF
+1.8 V t o +5 V
VLC
0.01 µF
+1.8 V to +5 V
RLOAD + 560
+3.3 V to +5 V
32
4,45
16
48
5.1 Ω
*
* Resistor may only be
used if VD is derived
from VA. If used, do not
drive any other logic
from VD
GND
31
ADC_M0
ADC_M1
44
43
6ADC_384x/256x
ADC_PDN
18
1 µF 0.01 µF
34
25
ADC_FILT+
ADC_VQ
0.01 µF
22 µF
12
11
5
ADC_LRCK
ADC_SCLK
SDOUT
Analog Input
Buff er
AINR
AINL
26
24
** Pu ll- u p to V LS f o r I2S
Pull- do w n to G ND f o r L J
VLS or GND **
µ C /
Mode
C onf iguration
Digital
Audio AOUTA2
RL
AOUTB2
RL
38
MUTEC2
3.3 µF 10 k ΩC
+
37
3.3 µF 10 k ΩC
560 Ω
+
36
AOUTA2
AOUTB2
OPTIONAL
MUTE
CIRCUIT
10 k Ω
10 k Ω
LOAD
LOAD
Figure 33. Typical Connection Diagram
CS42406
30 DS614PP5
4. APPLICATIONS
4.1 Single, Double, and Quad-Speed Modes
4.1.1 ADC Serial Port
The ADC’s internal to the CS42406 can support output sample rates from 2 kHz to 200 kHz, and a base
MCLK/ADC_LRCK ratio of either 256x or 384x. The proper speed mode can be determined by the desired
output sample rate and the external MCLK/ADC_LRCK ratio, as shown in Table 1 and Table 2. Please
see section 4.2 for a discussion on how to select the desired speed mode.
* Quad-Speed Mode, 64x only available in Master Mode.
Table 1. ADC Speed Modes and the Associated Output Sample Rates (Fs) for 256x Mode
* Quad Speed Mode, 96x only available in Master Mode.
Table 2. ADC Speed Modes and the Associated Output Sample Rates (Fs) for 384x Mode
4.1.2 DAC Serial Port
4.1.2a Stand Alone Mode
The DAC’s internal to the CS42406 operate in one of four operational modes determined by the DAC_Mx
pins when in Stand Alone Mode. Sample rates outside the specified range for each mode are not support-
ed. Refer to Table 3.
Speed Mode
MCLK /
ADC_LRCK Ratio
ADC_SCLK /
ADC_LRCK Ratio Output Sample Rate Range (kHz)
Single-Speed Mode 512x 32x, 48x, 64x 43 - 50
256x 32x, 48x, 64x 2 - 50
Double-Speed Mode 256x 32x, 48x, 64x 86 - 100
128x 32x, 48x, 64x 50 - 100
Quad-Speed Mode 128x 32x, 48x, 64x 172 - 200
64x* 64x 100 - 200
Speed Mode
MCLK/ADC_LRCK
Ratio
ADC_SCLK/ADC_
LRCK Ratio Output Sample Rate Range (kHz)
Single-Speed Mode 768x 32x, 48x, 64x 43 - 50
384x 32x, 48x, 64x 2 - 50
Double-Speed Mode 384x 32x, 48x 86 - 100
192x 32x, 48x 50 - 100
Quad-Speed Mode 192x 32x, 48x 172 - 200
96x* 48x 100 - 200
CS42406
31
4.1.2b Control Port Mode
The DAC’s operate in one of three operational modes determined by the FM bits (see section 6.1.4) in
Control Port mode. Sample rates outside the specified range for each mode are not supported.
4.2 ADC Serial Port Operation as Either a Clock Master or Slave
The CS42406 ADC serial port supports operation as either a clock master or slave. As a clock master, the
ADC_LRCK and ADC_SCLK pins are outputs with the left/right and serial clocks synchronously generated on-chip.
As a clock slave, the ADC_LRCK and ADC_SCLK pins are inputs and require the left/right and serial clocks to be
externally generated. The selection of clock master or slave is made via the ADC_Mx pins as shown in Table 5.
4.2.1 Operation as a Clock Master
As a clock master, ADC_LRCK and ADC_SCLK operate as outputs. The left/right and serial clocks are internally
derived from the master clock with the left/right clock equal to Fs and the serial clock equal to 64x Fs, as shown in
Figure 34.
DAC_M1 DAC_M0 Input Sample Rate (Fs) MODE
0 0 4 kHz - 50 kHz Single-Speed Mode (without De-emphasis)
0 1 32 kHz - 48 kHz Single-Speed Mode (with De-emphasis)
1 0 50 kHz - 100 kHz Double-Speed Mode
1 1 100 kHz - 200 kHz Quad-Speed Mode
Table 3. CS42406 Stand Alone DAC Operational Modes
FM1 FM0 Input Sample Rate (Fs) MODE
0 0 4 kHz - 50 kHz Single-Speed Mode
0 1 50 kHz - 100 kHz Double-Speed Mode
1 0 100 kHz - 200 kHz Quad-Speed Mode
1 1 Reserved Reserved
Table 4. CS42406 Control Port DAC Operational Modes
ADC_M1 ADC_M0 MODE
0 0 Clock Master, Single-Speed Mode
0 1 Clock Master, Double-Speed Mode
1 0 Clock Master, Quad-Speed Mode
1 1 Clock Slave, All Speed Modes
Table 5. CS42406 ADC Serial Port Mode Control
CS42406
32 DS614PP5
4.2.2 Operation as a Clock Slave
ADC_LRCK and ADC_SCLK operate as inputs in clock slave mode. It is recommended that the left/right clock be
synchronously derived from the master clock and must be equal to Fs. It is also recommended that the serial clock
be synchronously derived from the master clock and be equal to 64x Fs to maximize system performance. Please
refer to Table 1 and Table 2 for supported SCLK ratios.
A unique feature of the CS42406 ADC serial port is the automatic selection of either Single, Double or Quad-Speed
Mode when operating as a clock slave. The auto-mode selection feature supports all standard audio sample rates
from 2 to 200 kHz. However, there are ranges of non-standard audio sample rates that are not supported when op-
erating with a fast MCLK (512x/768x, 256x/384x, 128x/192x for Single, Double, and Quad-Speed Modes, respec-
tively). Please refer to Table 1 and Table 2 for supported sample rate ranges.
4.3 Digital Interface Format
4.3.1 DAC Serial Port
The CS42406 DAC serial port will accept audio samples in 1 of 4 digital interface formats in Stand Alone
Mode (as illustrated in Table 6), and 1 of 6 formats in Control Port mode (as illustrated in Table 7 on page
41).
÷ 128
÷ 256
÷ 64
ADC_M0ADC_M1
ADC_LRCK
Output
(Equal to Fsout)
Single
Speed
Quad
Speed
Double
Speed
00
01
10
÷ 2
÷ 4
÷ 1
ADC_SCLK
Output
Single
Speed
Quad
Speed
Double
Speed
00
01
10
÷ 1.5
÷ 1 0
1
MCLK
Auto-Select
÷ 2
÷ 3
0
1
Auto-Select
0
1
ADC_384x/256x
Figure 34. ADC Serial Port, Master Mode Clocking
CS42406
33
4.3.1a Stand Alone Mode
The desired format for the DAC serial port is selected via the DIF1 and DIF0 pins. For an illustration of the
required relationship between the DAC_LRCK, DAC_SCLK and SDINx, see Figures 28-30.
4.3.1b Control Port Mode
The desired format for the DAC serial port is selected via the DIF2, DIF1 and DIF0 bits in the Mode Control
2 register (see section 6.1.2). For an illustration of the required relationship between DAC_LRCK,
DAC_SCLK and SDINx, see Figures 28-30.
4.3.2 ADC Serial Port
The CS42406 ADC serial port supports both I²S and Left Justified serial audio formats. Upon start-up, the CS42406
will detect the logic level on SDOUT. A 10 kΩ pull-up resistor to VLS is needed to select I²S format, and a 10 kΩ
pull-down resistor to GND is needed to select Left Justified format. Please see Figures 28 and 29 for an illustration
of the required relationship between ADC_LRCK, ADC_SCLK, and SDOUT.
4.4 De-Emphasis Control
The CS42406 includes on-chip digital de-emphasis. Figure 35 shows the de-emphasis curve for Fs equal
to 44.1 kHz. The frequency response of the de-emphasis curve will scale proportionally with changes in
sample rate, Fs.
Notes: De-emphasis is only available in Single-Speed Mode.
4.4.1 Stand Alone Mode
The operational mode pins, DAC_M1 and DAC_M0, selects the 44.1 kHz de-emphasis filter. Please see
section 4.1.2a for the desired de-emphasis control.
4.4.2 Control Port Mode
The Mode Control bits selects either the 32, 44.1, or 48 kHz de-emphasis filter. Please see section 6.1.3
for the desired de-emphasis control.
DIF1 DIF0 DESCRIPTION FORMAT FIGURE
00 Left Justified, up to 24-bit Data 029
01 I²S, up to 24-bit Data 128
10 Right Justified, 16-bit Data 230
11 Right Justified, 24-bit Data 330
Table 6. DAC Digital Interface Format - Stand Alone Mode
Gain
dB
-10dB
0dB
Frequency
T2 = 15 µs
T1=50 µs
F1 F2
3.183 kHz 10.61 kHz
Figure 35. De-Emphasis Curve
CS42406
34 DS614PP5
4.5 Analog Connections
The analog modulator samples the input at 6.144 MHz. The digital filter will reject signals within the stop-
band of the filter. However, there is no rejection for input signals which are multiples of the input sampling
frequency (n *6.144 MHz), where n=0, 1, 2, ... Refer to Figure 36 which shows the suggested filter that
will attenuate any noise energy at 6.144 MHz, in addition to providing the optimum source impedance for
the modulators. The use of capacitors which have a large voltage coefficient (such as general purpose
ceramics) must be avoided since these can degrade signal linearity.
4.5.1 Capacitor Size on the Reference Pin (FILT+)
The CS42406 requires an external capacitance on the internal reference voltage pin, ADC_FILT+. The
size of this decoupling capacitor will affect the low frequency distortion performance as shown in Figure
37, with larger capacitor values used to optimize low frequency distortion performance.
*Place as close to
the CS42406 as
possible.
VA
+
-
4.7 µF
100 k Ω
100 k Ω
470 pF
C0G
634 Ω
91 Ω
2200 pF
C0G
AINL
AINR
CS42406
Input1
VA
+
-
4.7 µF
100 k Ω
100 k Ω
470 pF
C0G
634 Ω
91 Ω
2200 pF
C0G
Input 2
*
*
Figure 36. CS42406 Recommended Analog Input Buffer
47 uF
100 uF
22 uF
10 uF
6.8 uF
4.7 uF
3.3 uF
2.2 uF
1 uF
5.6 uF
Figure 37. CS42406 ADC: THD+N versus Frequency
CS42406
35
4.6 Recommended Power-up Sequence
4.6.1 Stand Alone Mode
1) Hold DAC_RST and ADC_PDN low until the power supplies and configuration pins are stable, and the
master and left/right clocks are locked to the appropriate frequencies. In this state, the control port is
reset to its default settings.
2) Bring DAC_RST and ADC_PDN high. The CS42406 DAC will remain in a low power state with
DAC_VQ low and will initiate the Stand Alone power-up sequence after approximately 512
DAC_LRCK cycles in Single-Speed Mode (1024 DAC_LRCK cycles in Double-Speed Mode, and
2048 DAC_LRCK cycles in Quad-Speed Mode). The CS42406 ADC will begin the power-up se-
quence immediately following ADC_PDN going high.
4.6.2 Control Port Mode
1) Hold DAC_RST and ADC_PDN low until the power supplies are stable, and the master and left/right
clocks are locked to the appropriate frequencies. In this state, the control port is reset to its default
settings.
2) Bring DAC_RST and ADC_PDN high. The CS42406 DAC will remain in a low power state with
DAC_VQ low.
3) Load the desired register settings while keeping the PDN bit set to 1.
4) Set the PDN bit to 0. This will initiate the power-up sequence for the DAC, which lasts approximately
50 µs when the POPG bit is set to 0. If the POPG bit is set to 1, see Section 4.7 for a complete de-
scription of power-up timing.
4.7 Popguard® Transient Control
The CS42406 uses a technique to minimize the effects of output transients during power-up and power-
down. This technology, when used with external DC-blocking capacitors in series with the audio outputs,
minimizes the audio transients commonly produced by single-ended single-supply converters. It is acti-
vated inside the CS42406 when the DAC_RST pin or PDN bit is enabled/disabled and requires no other
external control, aside from choosing the appropriate DC-blocking capacitors.
4.7.1 Power-up
When the device is initially powered-up, the audio outputs, AOUTAx and AOUTBx, are clamped to GND.
Following a delay of approximately 1000 DAC_LRCK cycles, each output begins to ramp toward the qui-
escent voltage. Approximately 10,000 DAC_LRCK cycles later, the outputs reach DAC_VQ and audio
output begins. This gradual voltage ramping allows time for the external DC-blocking capacitors to charge
to the quiescent voltage, minimizing the power-up transient.
4.7.2 Power-down
To prevent transients at power-down, the CS42406 must first enter its power-down state. When this oc-
curs, audio output ceases and the internal output buffers are disconnected from AOUTAx and AOUTBx.
In their place, a soft-start current sink is substituted which allows the DC-blocking capacitors to slowly dis-
charge. Once this charge is dissipated, the power to the device may be turned off and the system is ready
for the next power-on.
4.7.3 Discharge Time
To prevent an audio transient at the next power-on, the DC-blocking capacitors must fully discharge be-
fore turning on the power or exiting the power-down state. If full discharge does not occur, a transient will
occur when the audio outputs are initially clamped to GND. The time that the device must remain in the
CS42406
36 DS614PP5
power-down state is related to the value of the DC-blocking capacitance and the output load. For example,
with a 3.3 µF capacitor, the minimum power-down time will be approximately 0.4 seconds.
4.8 Mute Control
The Mute Control pins go high during power-up initialization, reset, muting (see section 6.1.1 and 6.4.1),
or if the MCLK to DAC_LRCK ratio is incorrect. These pins are intended to be used as control for external
mute circuits to prevent the clicks and pops that can occur in any single-ended single supply system.
Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute
minimum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system
designer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute
circuit. Please see the CDB42406 data sheet for a suggested mute circuit.
4.9 Grounding and Power Supply Arrangements
As with any high resolution converter, the CS42406 requires careful attention to power supply and ground-
ing arrangements if its potential performance is to be realized. Figure 33 shows the recommended power
arrangements, with VA, VD, VLS and VLC connected to clean supplies. If the ground planes are split be-
tween digital ground and analog ground, the GND pins of the CS42406 should be connected to the analog
ground plane.
All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted
coupling into the modulators. The CDB42406 evaluation board demonstrates the optimum layout and
power supply arrangements.
4.9.1 Capacitor Placement
Decoupling capacitors should be placed as close to the CS42406 as possible, with the low value ceramic
capacitor being the closest. To further minimize impedance, these capacitors should be located on the
same layer as the converter. If desired, all supply pins may be connected to the same supply, but a de-
coupling capacitor should still be placed on each supply pin and referenced to analog ground. Due to the
proximity of the two VD pins (pins 7 and 9), one set of decoupling capacitors will be sufficient for the digital
supply. Please refer to Figure 33.
4.10 Control Port Interface
The control port is used to load all the internal register settings (see section 6). The operation of the control
port may be completely asynchronous with the audio sample rate. However, to avoid potential interfer-
ence problems, the control port pins should remain static if no operation is required.
The control port operates in one of two modes: I²C or SPI.
Notes: MCLK must be applied during all I²C communication.
4.10.1 Memory Address Pointer (MAP)
The MAP byte precedes the control port register byte during a write operation and is not available again
until after a start condition is initiated. During a read operation the byte transmitted after the ACK will con-
tain the data of the register pointed to by the MAP (see sections 4.10.2a and 4.10.2b for write/read de-
tails).
76543210
INCR Reserved Reserved Reserved MAP3 MAP2 MAP1 MAP0
00000000
CS42406
37
4.10.1a INCR (Auto Map Increment)
The CS42406 has MAP auto increment capability enabled by the INCR bit (the MSB) of the MAP. If INCR
is set to 0, MAP will stay constant for successive I²C writes or reads and SPI writes. If INCR is set to 1,
MAP will auto increment after each byte is written, allowing block reads or writes of successive registers.
Default = ‘0’
0 - Disabled
1 - Enabled
4.10.1b MAP0-3 (Memory Address Pointer)
Default = ‘0000’
4.10.2 I²C Mode
In the I²C mode, data is clocked into and out of the bi-directional serial control data line, SDA, by the serial
control port clock, SCL. There is no CS pin. Pin AD0 enables the user to alter the chip address
(001000[AD0][R/W]) and should be tied to VLC or GND as required, before powering up the device. If the
device ever detects a high to low transition on the AD0/CS pin after power-up, SPI mode will be selected.
4.10.2a I²C Write
To write to the device, follow the procedure below while adhering to the control port timing as described
in “Switching Specifications - Control Port Interface” on page 27.
1) Initiate a START condition to the I²C bus followed by the address byte. The upper 6 bits must be
001000. The seventh bit must match the setting of the AD0 pin, and the eighth must be 0. The eighth
bit of the address byte is the R/W bit.
2) Wait for an acknowledge (ACK) from the part, then write to the memory address pointer, MAP. This
byte points to the register to be written.
3) Wait for an acknowledge (ACK) from the part, then write the desired data to the register pointed to by
the MAP.
4) If the INCR bit (see section 4.10.1a) is set to 1, repeat the previous step until all the desired registers
are written, then initiate a STOP condition to the bus.
5) If the INCR bit is set to 0 and further I²C writes to other registers are desired, it is necessary to repeat
the procedure detailed from step 1. If no further writes to other registers are desired, initiate a STOP
condition to the bus.
4.10.2b I²C Read
To read from the device, follow the procedure below while adhering to the control port Switching Specifi-
cations. During this operation it is first necessary to write to the device, specifying the appropriate register
through the MAP.
SDA
SCL
001000 AD0 W
Start
ACK MAP
1-8 ACK DATA
1-8 ACK
Stop
Figure 38. I²C Write
CS42406
38 DS614PP5
1) After writing to the MAP (see section 4.10.1), initiate a repeated START condition to the I²C bus fol-
lowed by the address byte. The upper 6 bits must be 001000. The seventh bit must match the setting
of the AD0 pin, and the eighth must be 1. The eighth bit of the address byte is the R/W bit.
2) Signal the end of the address byte by
not
issuing an acknowledge. The device will then transmit the
contents of the register pointed to by the MAP. The MAP will contain the address of the last register
written to the MAP.
3) If the INCR bit is set to 1, the device will continue to transmit the contents of successive registers. Con-
tinue providing a clock but do not issue an ACK on the bytes clocked out of the device. After all the
desired registers are read, initiate a STOP condition to the bus.
4) If the INCR bit is set to 0 and further I²C reads from other registers are desired, it is necessary to repeat
the procedure detailed from step 1. If no further reads from other registers are desired, initiate a STOP
condition to the bus.
4.10.3 SPI Mode
In SPI mode, data is clocked into the serial control data line, CDIN, by the serial control port clock, CCLK
(see Figure 40 for the clock to data relationship). There is no AD0 pin. Pin CS is the chip select signal and
is used to control SPI writes to the control port. When the device detects a high to low transition on the
AD0/CS pin after power-up, SPI mode will be selected. All signals are inputs and data is clocked in on the
rising edge of CCLK.
4.10.3a SPI Write
To write to the device, follow the procedure below while adhering to the control port Switching Specifica-
tions.
1) Bring CS low.
2) The address byte on the CDIN pin must then be 00100000.
3) Write to the memory address pointer, MAP. This byte points to the register to be written.
4) Write the desired data to the register pointed to by the MAP.
5) If the INCR bit (see section 4.10.1a) is set to 1, repeat the previous step until all the desired registers
are written, then bring CS high.
6) If the INCR bit is set to 0 and further SPI writes to other registers are desired, it is necessary to bring
CS high, and repeat the procedure detailed from step 1. If no further writes to other registers are de-
sired, bring CS high.
SDA
SCL
001000 AD0 W
Start
ACK MAP
1-8 ACK 001000 AD0 R
Repeated START
or
Aborted W RITE
ACK Data 1-8
(pointed to by MAP)
Data 1-8
(pointed to by MAP)
ACK
Stop
Figure 39. I²C Read
CS42406
39
MAP
MSB
LSB
DATA
byte 1 byte n
R/W
MAP = Memory Address Pointer
ADDRESS
CHIP
CDIN
CCLK
CS
0010000
Figure 40. SPI Write
CS42406
40 DS614PP5
5. REGISTER QUICK REFERENCE
Addr Function 7 6 5 4 3 2 1 0
1h Mode Control 1 AMUTE DIF2 DIF1 DIF0 DEM1 DEM0 FM1 FM0
default 10000000
2h Invert Signal Reserved Reserved INV_B3 INV_A3 INV_B2 INV_A2 INV_B1 INV_A1
default 00000000
3h Mixing Control P1 Reserved Reserved Reserved Reserved P1ATAPI3 P1ATAPI2 P1ATAPI1 P1ATAPI0
default 00001001
4h Mixing Control P2 Reserved Reserved Reserved Reserved P2ATAPI3 P2ATAPI2 P2ATAPI1 P2ATAPI0
default 00001001
5h Mixing Control P3 Reserved Reserved Reserved Reserved P3ATAPI3 P3ATAPI2 P3ATAPI1 P3ATAPI0
default 00001001
6h Volume Control A1 A1_MUTE A1_VOL6 A1_VOL5 A1_VOL4 A1_VOL3 A1_VOL2 A1_VOL1 A1_VOL0
default 00000000
7h Volume Control B1 B1_MUTE B1_VOL6 B1_VOL5 B1_VOL4 B1_VOL3 B1_VOL2 B1_VOL1 B1_VOL0
default 00000000
8h Volume Control A2 A2_MUTE A2_VOL6 A2_VOL5 A2_VOL4 A2_VOL3 A2_VOL2 A2_VOL1 A2_VOL0
default 00000000
9h Volume Control B2 B2_MUTE B2_VOL6 B2_VOL5 B2_VOL4 B2_VOL3 B2_VOL2 B2_VOL1 B2_VOL0
default 00000000
0Ah Volume Control A3 A3_MUTE A3_VOL6 A3_VOL5 A3_VOL4 A3_VOL3 A3_VOL2 A3_VOL1 A3_VOL0
default 00000000
0Bh Volume Control B3 B3_MUTE B3_VOL6 B3_VOL5 B3_VOL4 B3_VOL3 B3_VOL2 B3_VOL1 B3_VOL0
default 00000000
0Ch Mode Control 2 SZC1 SZC0 CPEN PDN POPG FREEZE Reserved SNGLVOL
default 10011000
CS42406
41
6. REGISTER DESCRIPTIONS
Note: All registers are read/write in I²C mode and write only in SPI, unless otherwise stated.
6.1 MODE CONTROL 1 (ADDRESS 01H)
6.1.1 AUTO-MUTE (AMUTE) BIT 7
Default = 1
0 - Disabled
1 - Enabled
Function:
The CS42406 DAC output will mute following the reception of 8192 consecutive audio samples of
static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is done
independently for each channel. The quiescent voltage on the output will be retained and the Mute
Control pin will go active during the mute period. The muting function is affected, similar to volume
control changes, by the Soft and Zero Cross bits in the Power and Muting Control register.
6.1.2 DIGITAL INTERFACE FORMAT (DIF) BIT 6-4
Default
= 000
- Format 0 (Left Justified, up to 24-bit data)
Function:
The required relationship between the DAC_LRCK, DAC_SCLK, and SDINx is defined by the Digital
Interface Format and the options are detailed in Figures 28-30.
76543210
AMUTE DIF2 DIF1 DIF0 DEM1 DEM0 FM1 FM0
10000000
DIF2 DIF1 DIF0 DESCRIPTION Format FIGURE
000
Left Justified, up to 24-bit data 028
001
I²S, up to 24-bit data 129
010
Right Justified, 16-bit data 230
011
Right Justified, 24-bit data 330
100
Right Justified, 20-bit data 430
101
Right Justified, 18-bit data 530
110
Reserved --
111
Reserved --
Table 7. Digital Interface Formats - Control Port Mode
CS42406
42 DS614PP5
6.1.3 DE-EMPHASIS CONTROL (DEM) BIT 3-2
Default = 00
00 - Disabled
01 - 44.1 kHz
10 - 48 kHz
11 - 32 kHz
Function:
Selects the appropriate digital filter to maintain the standard 15 µs/50 µs digital de-emphasis filter re-
sponse at 32, 44.1 or 48 kHz sample rates. (See Figure 35.)
Note: De-emphasis is only available in Single-Speed Mode.
6.1.4 FUNCTIONAL MODE (FM) BIT 1-0
Default = 00
00 - Single-Speed Mode (4 to 50 kHz sample rates)
01 - Double-Speed Mode (50 to 100 kHz sample rates)
10 - Quad-Speed Mode (100 to 200 kHz sample rates)
11 - Reserved
Function:
Selects the required range of input sample rates.
6.2 INVERT SIGNAL (ADDRESS 02H)
6.2.1 INVERT SIGNAL POLARITY (INV_XX) BIT 5-0
Default = 0
0 - Disabled
1 - Enabled
Function:
When enabled, these bits invert the signal polarity for each of their respective channels.
6.3 MIXING CONTROL PAIR 1 (CHANNELS A1 & B1) (ADDRESS 03H)
MIXING CONTROL PAIR 2 (CHANNELS A2 & B2) (ADDRESS 04H)
MIXING CONTROL PAIR 3 (CHANNELS A3 & B3) (ADDRESS 05H)
76543210
Reserved Reserved INV_B3 INV_A3 INV_B2 INV_A2 INV_B1 INV_A1
00000000
76543210
Reserved Reserved Reserved Reserved PxATAPI3 PxATAPI2 PxATAPI1 PxATAPI0
00001001
CS42406
43
6.3.1 ATAPI CHANNEL MIXING AND MUTING (ATAPI) BIT 3-0
Default = 1001 - AOUTAx = L, AOUTBx = R (Stereo)
Function:
The CS42406 implements the channel mixing functions of the ATAPI CD-ROM specification. Refer
to Table 8 and Figure 41 for additional information.
Note: All mixing functions occur prior to the digital volume control. Mixing only occurs in channel pairs.
ATAPI3 ATAPI2 ATAPI1 ATAPI0 AOUTAx AOUTBx
0000 MUTE MUTE
0001 MUTE R
0010 MUTE L
0011 MUTE [(L+R)/2]
0100 R MUTE
0101 R R
0110 R L
0111 R [(L+R)/2]
1000 L MUTE
1001 L R
1010 L L
1011 L [(L+R)/2]
1100[(L+R)/2] MUTE
1101[(L+R)/2] R
1110[(L+R)/2] L
1111[(L+R)/2] [(L+R)/2]
Table 8. ATAPI Decode
Σ
A Channel
Volume
Control Aout
A
Aout
B
Left Channel
Audio Data
Right Channel
Audio Data
B Channel
Volume
Control
& Mute
& Mute
Figure 41. ATAPI Block Diagram
CS42406
44 DS614PP5
6.4 VOLUME CONTROL (ADDRESSES 06H - 0BH)
6.4.1 MUTE (MUTE) BIT 7
Default = 0
0 - Disabled
1 - Enabled
Function:
The CS42406 DAC output converter output will mute when enabled. The quiescent voltage on the
output will be retained. The muting function is affected, similar to attenuation changes, by the Soft and
Zero Cross bits. The MUTECx pins will go active during the mute period if the Mute function is enabled
for both channels in the pair.
6.4.2 DAC VOLUME CONTROL (XX_VOL) BIT 6-0
Default = 0
Function:
The Digital Volume Control registers allow independent control of the signal levels in 1 dB increments
from 0 to -119 dB. Volume settings are decoded as shown in Table 9. The volume changes are im-
plemented as dictated by the Soft Ramp and Zero Cross bits. All volume settings less than -119 dB
are equivalent to enabling the MUTE bit.
6.5 MODE CONTROL 2 (ADDRESS 0CH)
6.5.1 SOFT RAMP AND ZERO CROSS CONTROL (SZC) BIT 7-6
Default = 10
00 - Immediate Change
01 - Zero Cross
10 - Soft Ramp
11 - Soft Ramp and Zero Cross
Function:
Immediate Change
When Immediate Change is selected all level changes will be implemented immediately in one step.
76543210
xx_MUTE xx_VOL6 xx_VOL5 xx_VOL4 xx_VOL3 xx_VOL2 xx_VOL1 xx_VOL0
00000000
Binary Code Decimal Value Volume Setting
0001010 10 -10 dB
0010100 20 -20 dB
0101000 40 -40 dB
0111100 60 -60 dB
1011010 90 -90 dB
Table 9. Example Digital Volume Settings
76543210
SZC1 SZC0 CPEN PDN POPG FREEZE RESERVED SNGLVOL
10011000
CS42406
45
Zero Cross
Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will
occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur
after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz input
sample rate) if the signal does not encounter a zero crossing. The zero cross function is independent-
ly monitored and implemented for each channel.
Soft Ramp
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally
ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 DAC_LRCK
periods.
Soft Ramp and Zero Cross
Soft Ramp and Zero Cross dictates that signal level changes, either by attenuation changes or mut-
ing, will occur in 1/8 dB steps and will be implemented on successive signal zero crossings. The 1/8
dB level changes will occur after timeout periods between 512 and 1024 sample periods (10.7 ms to
21.3 ms at 48 kHz input sample rate) if the signal does not encounter zero crossings. The zero cross
function is independently monitored and implemented for each channel.
6.5.2 CONTROL PORT ENABLE (CPEN) BIT 5
Default = 0
0 - Disabled
1 - Enabled
Function:
The Control Port will become active and reset to the default settings when this function is enabled.
6.5.3 POWER DOWN (PDN) BIT 4
Default = 1
0 - Disabled
1 - Enabled
Function:
The DAC will enter a low-power state when this function is enabled, but the contents of the control
registers will be retained in this mode. The power-down bit defaults to ‘enabled’ on power-up and must
be disabled before normal operation in Control Port mode can occur.
6.5.4 POPGUARD® TRANSIENT CONTROL (POPG) BIT 3
Default = 1
0 - Disabled
1 - Enabled
Function:
The PopGuard
®
Transient Control allows the quiescent voltage to slowly ramp to and from 0 volts to
the quiescent voltage during power-on or power-off when this function is enabled. Please see section
4.7 for implementation details.
CS42406
46 DS614PP5
6.5.5 FREEZE CONTROLS (FREEZE) BIT 2
Default = 0
0 - Disabled
1 - Enabled
Function:
This function allows modifications to be made to the registers without the changes taking effect until
the FREEZE is disabled. To have multiple changes in the control port registers take effect simulta-
neously, enable the FREEZE bit, make all register changes, then disable the FREEZE bit.
6.5.6 SINGLE VOLUME CONTROL (SNGLVOL) BIT 0
Default = 0
0 - Disabled
1 - Enabled
Function:
The individual channel volume levels are independently controlled by their respective Volume Control
Bytes when this function is disabled. When enabled, the volume on all channels is determined by the
A1 Channel Volume Control Byte, and the other Volume Control Bytes are ignored.
CS42406
47
7 PARAMETER DEFINITIONS
Dynamic Range
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made
with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale.
This technique ensures that the distortion components are below the noise level and do not affect the
measurement. This measurement technique has been accepted by the Audio Engineering Society,
AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels.
Total Harmonic Distortion + Noise
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured
at -1 and -20 dBFS as suggested in AES17-1991 Annex A.
Frequency Response
A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response
at 1 kHz. Units in decibels.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with no signal to the input under test and a full-scale signal applied to the other channel. Units in
decibels.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
Gain Error
The deviation from the nominal full-scale analog input for a full-scale digital output.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
Offset Error
The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.
CS42406
48 DS614PP5
8. PACKAGE DIMENSIONS
INCHES MILLIMETERS
DIM MIN NOM MAX MIN NOM MAX
A --- 0.055 0.063 --- 1.40 1.60
A1 0.002 0.004 0.006 0.05 0.10 0.15
B 0.007 0.009 0.011 0.17 0.22 0.27
D 0.343 0.354 0.366 8.70 9.0 BSC 9.30
D1 0.272 0.28 0.280 6.90 7.0 BSC 7.10
E 0.343 0.354 0.366 8.70 9.0 BSC 9.30
E1 0.272 0.28 0.280 6.90 7.0 BSC 7.10
e* 0.016 0.020 0.024 0.40 0.50 BSC 0.60
L 0.018 0.24 0.030 0.45 0.60 0.75
∝0.000° 4° 7.000° 0.00° 4° 7.00°
* Nominal pin pitch is 0.50 mm
Controlling dimension is mm.
JEDEC Designation: MS026
48L LQFP PACKAGE DRAWING
E1
E
D1
D
1
e
L
∝
B
A1
A
CS42406
49
9. REVISION HISTORY
Revision Date Changes
PP1 August 2003 Initial Release
PP2 March 2004
Added
Revision History Table.
Changed
“Gain Error” from ±5% to ±10% in the ADC Analog Characteristics.
Removed
“Inter Channel” and “Intra Channel Phase Deviation” specification on
page 11 and page 16.
Removed
ADC & DAC FILT+ “Output Impedance” and “Current Source Sink” spec-
ification on page 19.
Changed
maximum VOL from 13% to 15% on page 20.
Changed
MCLK min/max duty cycle from 40/60% to 45/55% on page 23.
Added
Figure 37 on page 34.
PP3 August 2004
Added
lead free part numbers.
PP4 December 2004
Corrected
typographical errors.
PP5 December 2004
Removed
automotive part
CS42406-DQZ
ordering availability and performance
specifications.
Added
Note 3 to 4 on page 8 limiting VA, VD and VL operation.
Modified
table “Switching Characteristics - ADC Serial Audio Port” on page 23 to
highlight 256x and 384x mode.
Added
“ADC_LRCK Frequency”, “SCLK Duty Cycle (Slave Mode)” and setup &
hold timing specifications in “Switching Characteristics - ADC Serial Audio Port” on
page 23.
Removed
ADC_SCLK high/low timing and the “ADC_SCLK falling to SDOUT valid”
specifications from “Switching Characteristics - ADC Serial Audio Port” on page 23.
Modified
Figures 24 to 27 on page 25 to reflect timing specifications.
Corrected
Typical Connection Diagram, Figure 33 on page 29.
Added
ADC_SCLK/ADC_LRCK ratio parameters in Table 1 to 2 on page 30.
Changed
recommended anti-aliasing capacitor value from 2700 pF to 2200 pF in
Figure 36 “CS42406 Recommended Analog Input Buffer” on page 34.
Table 10. Revision History
CS42406
50 DS614PP5
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find one nearest you go to http://www.cirrus.com/
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